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| | | | * | | | Check latches type one by oneMiodrag Milanovic2019-10-042-40/+25
| | | | * | | | Removed top module where not neededMiodrag Milanovic2019-10-044-37/+4
| | | | * | | | Test muxes synth one by oneMiodrag Milanovic2019-10-042-38/+39
| | | | * | | | Cleaned verilog code from not used definesMiodrag Milanovic2019-10-041-6/+0
| | | | * | | | Check for MULT18X18D, since that is working nowMiodrag Milanovic2019-10-042-14/+11
| | | | * | | | Check flops one by oneMiodrag Milanovic2019-10-044-71/+50
| | | | * | | | Removed alu and div_mod tests as agreedMiodrag Milanovic2019-10-044-57/+0
| | | | * | | | equiv_opt with -assertEddie Hung2019-09-301-3/+1
| | | | * | | | Update resource count for alu.ysEddie Hung2019-09-301-3/+3
| | | | * | | | Move $x to end as per 7f0eec8Eddie Hung2019-09-301-1/+1
| | | | * | | | Update fsm.ys resource countEddie Hung2019-09-301-3/+3
| | | | * | | | Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys i...Eddie Hung2019-09-3037-0/+801
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| | | | | * | | | Add comment to dpram test about related issue.SergeyDegtyar2019-09-181-0/+1
| | | | | * | | | adffs test update (equiv_opt -multiclock). div_mod test fixSergeyDegtyar2019-09-173-17/+12
| | | | | * | | | Remove stat command form shifter.ys testSergeyDegtyar2019-09-041-1/+1
| | | | | * | | | Fix ecp5 testsSergeyDegtyar2019-09-0411-2421/+26
| | | | | * | | | Uncomment sat command in memory.ys test.SergeyDegtyar2019-09-031-2/+1
| | | | | * | | | Add tests for ECP5 architectureSergeyDegtyar2019-09-0340-0/+3201
| | | | | | * | | hierarchy - proc reorderMiodrag Milanovic2019-10-184-9/+10
| | | | | | * | | Cleanup and formatingMiodrag Milanovic2019-10-044-2/+4
| | | | | | * | | split latches into separate checksMiodrag Milanovic2019-10-042-41/+24
| | | | | | * | | check muxes per typeMiodrag Milanovic2019-10-042-42/+37
| | | | | | * | | check ff's separatelyMiodrag Milanovic2019-10-042-26/+14
| | | | | | * | | Cleanup top modules and not used definesMiodrag Milanovic2019-10-045-44/+5
| | | | | | * | | remove alu testMiodrag Milanovic2019-10-042-36/+0
| | | | | | * | | Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosy...Miodrag Milanovic2019-10-0423-0/+536
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| | | | | | * | | Merge branch 'master' into SergeyDegtyar/anlogicSergey2019-10-01126-1686/+30035
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| | | | | | * | | | run-test.sh Move $x at end of line.Sergey2019-10-011-1/+1
| | | | | | * | | | Add new tests for Anlogic architectureSergeyDegtyar2019-09-2323-0/+536
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| | | | | | | * | hierarchy - proc reorderMiodrag Milanovic2019-10-186-13/+15
| | | | | | | * | FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3
| | | | | | | * | Split mux tests per typeMiodrag Milanovic2019-10-042-38/+36
| | | | | | | * | Split latch checkMiodrag Milanovic2019-10-042-45/+24
| | | | | | | * | Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12
| | | | | | | * | split rest od ff'sMiodrag Milanovic2019-10-043-30/+17
| | | | | | | * | Separate check for ff's typesMiodrag Milanovic2019-10-042-47/+48
| | | | | | | * | Cleaned testsMiodrag Milanovic2019-10-045-49/+4
| | | | | | | * | Remove not needed testsMiodrag Milanovic2019-10-046-75/+0
| | | | | | | * | Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys...Miodrag Milanovic2019-10-0431-0/+710
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| | | | | | | * | run-test.sh Move $x at end of line.Sergey2019-10-011-1/+1
| | | | | | | * | Merge branch 'master' into SergeyDegtyar/efinixSergey2019-10-01126-1686/+30035
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| | | | | | | * | Add new tests for Efinix architecture.SergeyDegtyar2019-09-2331-0/+710
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* | | | | | | | Change smtbmc "Warmup failed" status to "PREUNSAT"Clifford Wolf2019-10-031-14/+14
* | | | | | | | Update ABC to git rev 623b5e8Clifford Wolf2019-10-031-1/+1
* | | | | | | | Bump versionClifford Wolf2019-10-031-1/+1
* | | | | | | | Merge pull request #1419 from YosysHQ/eddie/lazy_deriveClifford Wolf2019-10-032-35/+59
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| * | | | | | | | Fix for svinterfacesEddie Hung2019-09-301-2/+8
| * | | | | | | | module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-302-33/+51
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* | | | | | | | Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-032-6/+50
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| * | | | | | | | Add quick testEddie Hung2019-09-301-0/+10
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