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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 15:14:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 15:14:41 -0700 |
| commit | eeb86247c59f7ea7f98c05eaa456d0ebe041d149 (patch) | |
| tree | 16c7ea2ed62c3587e3bf706968ff8cda8889b828 | |
| parent | 0bbd1b63648f621dae92bcd5963e387eff66f685 (diff) | |
| download | yosys-eeb86247c59f7ea7f98c05eaa456d0ebe041d149.tar.gz yosys-eeb86247c59f7ea7f98c05eaa456d0ebe041d149.tar.bz2 yosys-eeb86247c59f7ea7f98c05eaa456d0ebe041d149.zip | |
Update fsm.ys resource count
| -rw-r--r-- | tests/ecp5/fsm.ys | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index bdd910163..36b10c0ce 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -8,7 +8,7 @@ equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:L6MUX21 -select -assert-count 15 t:LUT4 -select -assert-count 6 t:PFUMX -select -assert-count 6 t:TRELLIS_FF +select -assert-count 13 t:LUT4 +select -assert-count 5 t:PFUMX +select -assert-count 5 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D |