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author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 12:51:45 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 12:51:45 +0200 |
commit | 2c3e14024637bed14d8e8142f4d05c471630dbf7 (patch) | |
tree | 1d8a51f3bfa0b63556e43c31f52c7ce500b43dca | |
parent | 3de7889d08d0b02f1af6b9027b6e753eb0f6f490 (diff) | |
download | yosys-2c3e14024637bed14d8e8142f4d05c471630dbf7.tar.gz yosys-2c3e14024637bed14d8e8142f4d05c471630dbf7.tar.bz2 yosys-2c3e14024637bed14d8e8142f4d05c471630dbf7.zip |
split rest od ff's
-rw-r--r-- | tests/efinix/adffs.ys | 3 | ||||
-rw-r--r-- | tests/efinix/dffs.v | 22 | ||||
-rw-r--r-- | tests/efinix/dffs.ys | 22 |
3 files changed, 17 insertions, 30 deletions
diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys index d0be205d5..3471a0a80 100644 --- a/tests/efinix/adffs.ys +++ b/tests/efinix/adffs.ys @@ -45,9 +45,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:EFX_FF select -assert-count 1 t:EFX_GBUFCE - -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE select -assert-count 1 t:EFX_LUT4 select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/dffs.v b/tests/efinix/dffs.v index d97840c43..3418787c9 100644 --- a/tests/efinix/dffs.v +++ b/tests/efinix/dffs.v @@ -13,25 +13,3 @@ module dffe if ( en ) q <= d; endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/efinix/dffs.ys b/tests/efinix/dffs.ys index 557dfd3d0..fe8d93123 100644 --- a/tests/efinix/dffs.ys +++ b/tests/efinix/dffs.ys @@ -1,12 +1,24 @@ read_verilog dffs.v -hierarchy -top top +design -save read + proc -flatten +hierarchy -top dff equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D + +design -load read +proc +hierarchy -top dffe +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF select -assert-count 1 t:EFX_GBUFCE -select -assert-count 2 t:EFX_FF select -assert-count 1 t:EFX_LUT4 -select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D + +select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D |