| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | greenpak4: Added GP_DFFxI cells | Andrew Zonenberg | 2016-08-14 | 2 | -0/+68 |
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| * | greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6) | Andrew Zonenberg | 2016-08-13 | 1 | -10/+10 |
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| * | Merge pull request #198 from whitequark/master | Clifford Wolf | 2016-08-11 | 1 | -0/+2 |
| |\ | | | | | synth_greenpak4: use attrmvcp to move LOC from wires to cells | ||||
| | * | synth_greenpak4: use attrmvcp to move LOC from wires to cells. | whitequark | 2016-08-10 | 1 | -0/+2 |
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| * | Only allow posedge/negedge with 1 bit wide signals | Clifford Wolf | 2016-08-10 | 1 | -0/+2 |
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| * | Fixed some compiler warnings in attrmap command | Clifford Wolf | 2016-08-10 | 1 | -4/+4 |
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| * | Added "attrmap" command | Clifford Wolf | 2016-08-09 | 3 | -0/+253 |
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| * | Added log_const() API | Clifford Wolf | 2016-08-09 | 2 | -0/+19 |
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| * | Added "attrmvcp" pass | Clifford Wolf | 2016-08-09 | 2 | -0/+138 |
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| * | Use /proc/self/exe on Cygwin as well. | Yury Gribov | 2016-08-08 | 1 | -1/+1 |
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| * | Undo "preserve wire attributes in iopadmap" change (it was OK before) | Clifford Wolf | 2016-08-08 | 1 | -1/+1 |
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| * | Added "test_autotb -seed" (and "autotest.sh -S") | Clifford Wolf | 2016-08-06 | 2 | -5/+12 |
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| * | preserve wire attributes in iopadmap | Clifford Wolf | 2016-08-06 | 1 | -1/+1 |
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| * | Fixed bug in parsing real constants | Clifford Wolf | 2016-08-06 | 1 | -4/+4 |
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| * | Added "insbuf" command | Clifford Wolf | 2016-08-02 | 2 | -0/+95 |
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| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2016-07-30 | 16 | -22/+162 |
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| | * | Added $initstate support to smtbmc flow | Clifford Wolf | 2016-07-27 | 3 | -2/+19 |
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| | * | Added SatGen support for $anyconst | Clifford Wolf | 2016-07-27 | 1 | -0/+22 |
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| | * | Removed $predict support from SatGen | Clifford Wolf | 2016-07-27 | 1 | -9/+0 |
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| | * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 7 | -2/+83 |
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| | * | Added "read_verilog -dump_rtlil" | Clifford Wolf | 2016-07-27 | 5 | -9/+38 |
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| * | | Added "write_verilog -defparam" | Clifford Wolf | 2016-07-30 | 1 | -2/+21 |
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| * | | Added "write_verilog -nodec -nostr" | Clifford Wolf | 2016-07-30 | 1 | -4/+27 |
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| * | Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() | Clifford Wolf | 2016-07-25 | 3 | -3/+3 |
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| * | Fixed a verilog parser memory leak | Clifford Wolf | 2016-07-25 | 1 | -0/+1 |
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| * | Fixed parsing of empty positional cell ports | Clifford Wolf | 2016-07-25 | 1 | -2/+31 |
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| * | Improvements in CellEdgesDatabase | Clifford Wolf | 2016-07-24 | 3 | -16/+167 |
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| * | Added CellEdgesDatabase API | Clifford Wolf | 2016-07-24 | 4 | -1/+250 |
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| * | Moved SatHelper::setup_init() code to SatHelper::setup() | Clifford Wolf | 2016-07-24 | 1 | -97/+92 |
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| * | Added $initstate support to "sat" command | Clifford Wolf | 2016-07-23 | 1 | -13/+12 |
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| * | No tristate warning message for "read_verilog -lib" | Clifford Wolf | 2016-07-23 | 3 | -8/+11 |
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| * | Added satgen initstate support | Clifford Wolf | 2016-07-22 | 1 | -0/+27 |
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| * | Using $initstate in "initial assume" and "initial assert" | Clifford Wolf | 2016-07-21 | 1 | -1/+6 |
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| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 7 | -4/+54 |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 16 | -32/+28 |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 16 | -19/+82 |
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| * | Added examples/smtbmc | Clifford Wolf | 2016-07-13 | 2 | -0/+30 |
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| * | Merge pull request #191 from whitequark/json-module-attributes | Clifford Wolf | 2016-07-13 | 1 | -2/+6 |
| |\ | | | | | write_json: also write module attributes | ||||
| | * | write_json: also write module attributes. | whitequark | 2016-07-12 | 1 | -2/+6 |
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| * | | Merge pull request #193 from azonenberg/master | Clifford Wolf | 2016-07-13 | 2 | -2/+9 |
| |\ \ | | | | | | | Removed splitnets in synth_greenpak4, added GP_DAC, refactored GP_BANDGAP | ||||
| | * \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-07-12 | 1 | -2/+5 |
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| * | | | Minor bugfix in FSM reset state detection | Clifford Wolf | 2016-07-12 | 1 | -2/+5 |
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| | * | Added GP_DAC cell | Andrew Zonenberg | 2016-07-11 | 1 | -0/+8 |
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| | * | Removed VOUT port of GP_BANDGAP | Andrew Zonenberg | 2016-07-11 | 1 | -1/+1 |
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| | * | Removed splitnets in prep for new gp4par parser | Andrew Zonenberg | 2016-07-11 | 1 | -1/+0 |
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| * | Yosys-smtbmc: Support for hierarchical VCD dumping | Clifford Wolf | 2016-07-11 | 2 | -23/+59 |
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| * | Moved smt2 yosys info parsing from smtbmc.py to smtio.py | Clifford Wolf | 2016-07-11 | 3 | -16/+56 |
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| * | Added "prep -auto-top" and "synth -auto-top" | Clifford Wolf | 2016-07-11 | 2 | -6/+23 |
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| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2016-07-10 | 1 | -0/+26 |
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| | * | Merge pull request #189 from whitequark/master | Clifford Wolf | 2016-07-10 | 1 | -0/+26 |
| | |\ | | | | | | | greenpak4: add GP_COUNT{8,14}_ADV cells | ||||
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index : iCE40/yosys | |
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