aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* xilinx: add delays to INVEddie Hung2020-02-271-0/+3
* Make TimingInfo::TimingInfo(SigBit) constructor explicitEddie Hung2020-02-273-8/+9
* TimingInfo: index by (port_name,offset)Eddie Hung2020-02-272-12/+23
* Fix spacingEddie Hung2020-02-272-68/+68
* More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
* Cleanup testsEddie Hung2020-02-272-1/+1
* Update bug1630.ys to use -lut 4 instead of lut fileEddie Hung2020-02-271-1/+1
* Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
* abc9_ops: still emit delay table even box has no timingEddie Hung2020-02-271-3/+1
* write_xaiger: add comment about arrival times of flop outputsEddie Hung2020-02-271-0/+1
* abc9_ops: demote lack of box timing info to warningEddie Hung2020-02-271-2/+4
* Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-276-651/+530
* abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-272-25/+22
* abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-273-97/+65
* abc9_ops: add and use new TimingInfo structEddie Hung2020-02-272-70/+214
* Fix tests/arch/xilinx/fsm.ys to count flops onlyEddie Hung2020-02-271-9/+3
* Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
* ice40: fix specify for inverted clocksEddie Hung2020-02-271-27/+27
* Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
* Update simple_abc9 testsEddie Hung2020-02-273-5/+8
* abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-274-104/+114
* ice40: specify fixesEddie Hung2020-02-273-66/+66
* abc9_ops: sort LUT delays to be ascendingEddie Hung2020-02-271-1/+4
* ice40: move over to specify blocks for -abc9Eddie Hung2020-02-2710-164/+1344
* synth_ecp5: use +/abc9_model.vEddie Hung2020-02-271-1/+1
* Update xilinx for ABC9Eddie Hung2020-02-273-20/+16
* Create +/abc9_model.v for $__ABC9_{DELAY,FF_}Eddie Hung2020-02-272-0/+11
* abc9_ops: output LUT areaEddie Hung2020-02-271-6/+6
* ecp5: remove small LUT entriesEddie Hung2020-02-271-24/+6
* abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTsEddie Hung2020-02-271-18/+33
* Fix commented out specify statementEddie Hung2020-02-271-6/+6
* xilinx: improve specify functionalityEddie Hung2020-02-278-466/+547
* ecp5: deprecate abc9_{arrival,required} and *.{lut,box}Eddie Hung2020-02-277-86/+120
* xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-273-347/+670
* Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-278-466/+268
* abc9_ops: assert on $specify2 propertiesEddie Hung2020-02-271-0/+3
* abc9_ops: -prep_box, to be called onceEddie Hung2020-02-273-51/+50
* abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-274-10/+200
* Merge pull request #1709 from rqou/coolrunner2_counterClaire Wolf2020-02-274-97/+519
|\
| * coolrunner2: Use extract_counter to optimize countersR. Ou2020-02-173-0/+165
| * extract_counter: Implement extracting up countersR. Ou2020-02-171-65/+247
| * extract_counter: Add support for inverted clock enableR. Ou2020-02-171-8/+28
| * extract_counter: Fix clock enableR. Ou2020-02-171-1/+3
| * extract_counter: Fix outputting count to module portR. Ou2020-02-171-8/+20
| * extract_counter: Allow forbidding async resetR. Ou2020-02-171-2/+17
| * extract_counter: Refactor out extraction settings into structR. Ou2020-02-171-17/+43
* | Merge pull request #1708 from rqou/coolrunner2-buf-fixClaire Wolf2020-02-274-54/+163
|\ \
| * | coolrunner2: Separate and improve buffer cell insertion passR. Ou2020-02-164-54/+163
| |/
* | xilinx: mark IOBUFDSE3 IOB pin as externalPiotr Binkowski2020-02-272-1/+2
* | Merge pull request #1705 from YosysHQ/logger_passMiodrag Milanović2020-02-266-2/+303
|\ \