| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | opt_clean: Remove init attribute bits together with removed DFFs. | Marcelina Kościelnicka | 2021-03-15 | 2 | -11/+24 |
| * | rtlil: Disallow 0-width chunks in SigSpec. | Marcelina Kościelnicka | 2021-03-15 | 2 | -18/+63 |
| * | Merge pull request #2658 from zachjs/parameters-across-files | whitequark | 2021-03-14 | 3 | -1/+21 |
| |\ |
|
| | * | sv: allow globals in one file to depend on globals in another | Zachary Snow | 2021-03-12 | 3 | -1/+21 |
| |/ |
|
| * | Merge pull request #2653 from zachjs/global-parameter | whitequark | 2021-03-12 | 2 | -0/+18 |
| |\ |
|
| | * | verilog: disallow overriding global parameters | Zachary Snow | 2021-03-11 | 2 | -0/+18 |
| * | | Merge pull request #2642 from whitequark/cxxrtl-noproc-fixes | whitequark | 2021-03-11 | 1 | -17/+29 |
| |\ \ |
|
| | * | | cxxrtl: don't assert on edge sync rules tied to a constant. | whitequark | 2021-03-07 | 1 | -0/+4 |
| | * | | cxxrtl: allow `always` sync rules in debug_eval. | whitequark | 2021-03-07 | 1 | -17/+25 |
| * | | | Add _pm.h files to GENLIST, fixes vcxsrc target | Miodrag Milanovic | 2021-03-11 | 1 | -0/+9 |
| | |/
|/| |
|
| * | | Replace assert in xaiger with more useful error message | Dan Ravensloft | 2021-03-10 | 1 | -1/+2 |
| * | | Merge pull request #2643 from zachjs/fix-param-no-default-log | whitequark | 2021-03-08 | 1 | -1/+1 |
| |\ \ |
|
| | * | | Fix param without default log line | Zachary Snow | 2021-03-07 | 1 | -1/+1 |
| * | | | Bump version | Marcelina Kościelnicka | 2021-03-08 | 1 | -1/+1 |
| * | | | memory_dff: Remove now-useless write port handling. | Marcelina Kościelnicka | 2021-03-08 | 6 | -82/+19 |
| * | | | verilog: Use proc memory writes in the frontend. | Marcelina Kościelnicka | 2021-03-08 | 5 | -29/+94 |
| * | | | Add support for memory writes in processes. | Marcelina Kościelnicka | 2021-03-08 | 16 | -43/+245 |
| * | | | sim: Avoid a crash on empty cell connection. | Marcelina Kościelnicka | 2021-03-08 | 1 | -1/+1 |
| * | | | proc_dff: Fix emitted FF when a register is not assigned in async reset | Marcelina Kościelnicka | 2021-03-08 | 2 | -0/+27 |
| * | | | memory_dff: Remove code looking for $mux cells. | Marcelina Kościelnicka | 2021-03-08 | 1 | -56/+12 |
| * | | | tests/bram: Do not generate write address collisions. | Marcelina Kościelnicka | 2021-03-08 | 1 | -5/+23 |
| |/ / |
|
| * | | Replace assert in abc9_ops with more useful error message | Dan Ravensloft | 2021-03-07 | 1 | -1/+9 |
| * | | Merge pull request #2626 from zachjs/param-no-default | whitequark | 2021-03-07 | 12 | -5/+225 |
| |\ \ |
|
| | * | | sv: support for parameters without default values | Zachary Snow | 2021-03-02 | 12 | -5/+225 |
| * | | | Merge pull request #2632 from zachjs/width-limit | whitequark | 2021-03-07 | 3 | -0/+39 |
| |\ \ \ |
|
| | * | | | verilog: impose limit on maximum expression width | Zachary Snow | 2021-03-04 | 3 | -0/+39 |
| * | | | | sv: fix some edge cases for unbased unsized literals | Zachary Snow | 2021-03-06 | 4 | -1/+70 |
| * | | | | proc_clean: Fix empty case removal conditions. | Marcelina Kościelnicka | 2021-03-06 | 1 | -10/+21 |
| | |_|/
|/| | |
|
| * | | | Remove a few functions that, in fact, did not exist in the first place. | Marcelina Kościelnicka | 2021-03-06 | 2 | -3/+1 |
| * | | | Replace assert in addModule with more useful error message | Dan Ravensloft | 2021-03-06 | 1 | -1/+2 |
| * | | | Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addr | whitequark | 2021-03-05 | 1 | -1/+3 |
| |\ \ \ |
|
| | * | | | cxxrtl: follow aliases to outlines when emitting $memrd.ADDR. | whitequark | 2021-03-05 | 1 | -1/+3 |
| | |/ / |
|
| * | | | Merge pull request #2634 from whitequark/cxxrtl-debug-wire-types | whitequark | 2021-03-05 | 1 | -0/+46 |
| |\ \ \ |
|
| | * | | | cxxrtl: add pass debug flag to show assigned wire types. | whitequark | 2021-03-05 | 1 | -0/+46 |
| | |/ / |
|
| * | | | Merge pull request #2633 from whitequark/cxxrtl-no-top | whitequark | 2021-03-05 | 1 | -1/+1 |
| |\ \ \
| |/ /
|/| | |
|
| | * | | cxxrtl: don't crash on empty designs. | whitequark | 2021-03-05 | 1 | -1/+1 |
| |/ / |
|
| * | | Update command-reference-manual.tex | Claire Xen | 2021-03-04 | 1 | -4/+4 |
| * | | Update README | Claire Xen | 2021-03-04 | 1 | -4/+4 |
| |/ |
|
| * | Merge pull request #2620 from zachjs/port-int-types | whitequark | 2021-03-01 | 3 | -2/+64 |
| |\ |
|
| | * | verilog: fix sizing of ports with int types in module headers | Zachary Snow | 2021-03-01 | 3 | -2/+64 |
| * | | Bump version | Marcelina Kościelnicka | 2021-03-01 | 1 | -1/+1 |
| |/ |
|
| * | verilog: fix handling of nested ifdef directives | Zachary Snow | 2021-03-01 | 8 | -11/+197 |
| * | Set aside extraneous tests in simple_abc9 test suite | Zachary Snow | 2021-03-01 | 2 | -0/+19 |
| * | Merge pull request #2523 from tomverbeure/define_synthesis | Claire Xen | 2021-03-01 | 1 | -3/+12 |
| |\ |
|
| | * | Fix indents. | Tom Verbeure | 2021-01-04 | 1 | -2/+2 |
| | * | Add -nosynthesis flag for read_verilog command. | Tom Verbeure | 2021-01-04 | 1 | -3/+12 |
| * | | Merge pull request #2524 from bkbncn/patch-1 | Claire Xen | 2021-03-01 | 1 | -0/+1 |
| |\ \ |
|
| | * | | Add boost-python3 | Xiangyu Xu | 2021-01-04 | 1 | -0/+1 |
| | |/ |
|
| * | | Merge pull request #2617 from RobertBaruch/doc | whitequark | 2021-03-01 | 1 | -1/+1 |
| |\ \ |
|
| | * | | RTLIL Documentation: switch in process is optional | Robert Baruch | 2021-02-27 | 1 | -1/+1 |
