diff options
| -rw-r--r-- | passes/opt/opt_clean.cc | 4 | ||||
| -rw-r--r-- | tests/opt/opt_clean_init.ys | 31 |
2 files changed, 24 insertions, 11 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 883374cf6..c66f45308 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -21,6 +21,7 @@ #include "kernel/sigtools.h" #include "kernel/log.h" #include "kernel/celltypes.h" +#include "kernel/ffinit.h" #include <stdlib.h> #include <stdio.h> #include <set> @@ -101,6 +102,7 @@ void rmunused_module_cells(Module *module, bool verbose) pool<SigBit> used_raw_bits; dict<SigBit, pool<Cell*>> wire2driver; dict<SigBit, vector<string>> driver_driver_logs; + FfInitVals ffinit(&sigmap, module); SigMap raw_sigmap; for (auto &it : module->connections_) { @@ -193,6 +195,8 @@ void rmunused_module_cells(Module *module, bool verbose) if (verbose) log_debug(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str()); module->design->scratchpad_set_bool("opt.did_something", true); + if (RTLIL::builtin_ff_cell_types().count(cell->type)) + ffinit.remove_init(cell->getPort(ID::Q)); module->remove(cell); count_rm_cells++; } diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys index 0d567608d..7933f3e17 100644 --- a/tests/opt/opt_clean_init.ys +++ b/tests/opt/opt_clean_init.ys @@ -1,13 +1,22 @@ -logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1 -logger -expect-no-warnings -read_verilog <<EOT -module top; -(* init=1'b0 *) wire w = 1'b0; -(* init=1'bx *) wire x = 1'b0; -(* init=1'b1 *) wire y = 1'b0; -(* init=1'b0 *) wire z = 1'bx; +read_verilog << EOT +module top(...); + +input [1:0] D; +input C; +output O; +reg [1:0] Q; + +initial Q = 0; + +always @(posedge C) + Q <= D; + +assign O = Q[1]; + endmodule EOT -clean -select -assert-count 1 a:init -select -assert-count 1 w:y a:init %i + +synth +check -assert -initdrv + +select -assert-count 1 a:init=2'b0x |