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* Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-056-308/+276
* Error if $currQ not foundEddie Hung2019-10-051-0/+4
* abc -> abc9Eddie Hung2019-10-041-3/+3
* Fix from mergeEddie Hung2019-10-041-1/+1
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-048-184/+33
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| * Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-042-5/+19
| * Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
| * Fix xilinx_dsp for unsigned extensionsEddie Hung2019-10-041-1/+3
| * Fix for SigSpec() == SigSpec(State::Sx, 0) to be true againEddie Hung2019-10-041-0/+6
| * Add Const::{begin,end,empty}()Eddie Hung2019-10-041-0/+3
* | Use read_args for read_verilogEddie Hung2019-10-041-3/+6
* | Fix merge issuesEddie Hung2019-10-046-21/+14
* | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-0434-361/+376
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| * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0434-305/+313
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| * Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-045-31/+4
| * OopsEddie Hung2019-10-041-1/+1
| * Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-0320-86/+374
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| * Change smtbmc "Warmup failed" status to "PREUNSAT"Clifford Wolf2019-10-031-14/+14
| * Update ABC to git rev 623b5e8Clifford Wolf2019-10-031-1/+1
| * Bump versionClifford Wolf2019-10-031-1/+1
| * Merge pull request #1419 from YosysHQ/eddie/lazy_deriveClifford Wolf2019-10-032-35/+59
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| | * Fix for svinterfacesEddie Hung2019-09-301-2/+8
| | * module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-302-33/+51
| * | Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-032-6/+50
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| | * | Add quick testEddie Hung2019-09-301-0/+10
| | * | Add -select option to aigmapEddie Hung2019-09-301-6/+40
| * | | Merge pull request #1429 from YosysHQ/clifford/checkmappedClifford Wolf2019-10-032-27/+56
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| | * | | Add "check -allow-tbuf"Clifford Wolf2019-10-031-8/+22
| | * | | Add "check -mapped"Clifford Wolf2019-10-022-21/+36
| * | | | Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16David Shah2019-10-036-2/+184
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| | * | | | ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
| | * | | | ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
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| * | | | Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wireEddie Hung2019-10-022-0/+32
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| | * | | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
| | * | | | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
| | * | | | Add testEddie Hung2019-09-301-0/+16
| | * | | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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| * | | | log_dump() to support State enumEddie Hung2019-10-023-0/+6
| * | | | Merge pull request #1428 from YosysHQ/clifford/fixbtorClifford Wolf2019-10-021-6/+9
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| | * | | Fix btor back-end to use "state" instead of "input" for undef init bitsClifford Wolf2019-10-021-6/+9
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| * | | Merge pull request #1426 from YosysHQ/mmicko/fix_environMiodrag Milanović2019-10-011-0/+2
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| | * | Define environ, fixes #1424Miodrag Milanovic2019-10-011-0/+2
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| * / Fix typoEddie Hung2019-09-301-1/+1
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* | EnglishEddie Hung2019-10-031-3/+3
* | More fixesEddie Hung2019-10-011-16/+16
* | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48
* | No need to punch ports at allEddie Hung2019-09-302-13/+24
* | Resolve FIXME on calling proc just onceEddie Hung2019-09-301-2/+2
* | Cleanup $currQ from aigerparseEddie Hung2019-09-301-2/+0
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