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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 16:37:29 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 16:37:29 -0700 |
| commit | 390b960c8c646018c1f6cddfec5fc2d528d42fa4 (patch) | |
| tree | bb14e6c2ed5c08ed79b0ffe0c453646fd6ae4947 | |
| parent | f9bb3352944275acc6e82eaf53aebf3c964f68c4 (diff) | |
| download | yosys-390b960c8c646018c1f6cddfec5fc2d528d42fa4.tar.gz yosys-390b960c8c646018c1f6cddfec5fc2d528d42fa4.tar.bz2 yosys-390b960c8c646018c1f6cddfec5fc2d528d42fa4.zip | |
Resolve FIXME on calling proc just once
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 6e424d517..ce057566c 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1117,8 +1117,8 @@ struct Abc9Pass : public Pass { auto derived_name = inst_module->derive(design, cell->parameters); auto derived_module = design->module(derived_name); log_assert(derived_module); - // FIXME: call once - Pass::call_on_module(design, derived_module, "proc"); + if (derived_module->has_processes()) + Pass::call_on_module(design, derived_module, "proc"); SigMap derived_sigmap(derived_module); Wire *currQ = derived_module->wire("\\$currQ"); |