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* | Fixed proc_{self,share}_dirname error handlingClifford Wolf2014-08-171-4/+2
* | Makefile fixesClifford Wolf2014-08-171-1/+4
* | Improved AST ProcessGenerator performanceClifford Wolf2014-08-171-3/+3
* | Improved sig.remove2() performanceClifford Wolf2014-08-171-2/+11
* | Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-173-24/+22
* | Added stackmap<> containerClifford Wolf2014-08-172-2/+109
* | Renamed toposort.h to utils.hClifford Wolf2014-08-173-2/+2
* | Added module->uniquify()Clifford Wolf2014-08-165-15/+29
* | Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-161-4/+4
* | Multiply using a carry-save accumulatorClifford Wolf2014-08-161-5/+45
* | Added "test_cell -s <seed>"Clifford Wolf2014-08-161-5/+17
* | AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-161-41/+26
* | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-168-48/+399
* | Added CellTypes::cell_evaluable()Clifford Wolf2014-08-161-31/+37
* | Changes in techmap $__alu interfaceClifford Wolf2014-08-161-17/+17
* | Added "opt -fast"Clifford Wolf2014-08-161-19/+45
* | Added log_spacer()Clifford Wolf2014-08-163-2/+20
* | Bugfix in iopadmapClifford Wolf2014-08-151-1/+3
* | Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-156-39/+38
* | Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-1519-47/+47
* | Removed old doc references to $safe_pmuxClifford Wolf2014-08-152-5/+1
* | More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-154-10/+22
* | Added Frontend "+/" filename syntax for files from proc_share_dirClifford Wolf2014-08-151-1/+4
* | document "techmap -map %<design-name>"Clifford Wolf2014-08-151-0/+3
* | Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-151-1/+1
* | Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-143-11/+20
* | Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-143-21/+31
* | Added sig.{replace,remove,extract} variants for std::{map,set} patternClifford Wolf2014-08-142-25/+64
* | Fixed line numbers when using here-doc macrosClifford Wolf2014-08-141-4/+9
* | Fixed handling of task outputsClifford Wolf2014-08-141-2/+4
* | Simplified $__arraymul techmap ruleClifford Wolf2014-08-141-7/+13
* | Added module->portsClifford Wolf2014-08-149-10/+23
* | Refactoring of CellType classClifford Wolf2014-08-143-155/+139
* | RIP $safe_pmuxClifford Wolf2014-08-1416-98/+21
* | Some improvements in FSM mapping and recodingClifford Wolf2014-08-143-9/+18
* | Added "abc -D" for setting delay targetClifford Wolf2014-08-141-5/+18
* | Updated ABC to 4935c2b946deClifford Wolf2014-08-141-1/+1
* | Added techmap support for actual lookahead carry unitClifford Wolf2014-08-131-22/+73
* | Preparations for lookahead ALU support in techmap.vClifford Wolf2014-08-131-28/+92
* | Filter ANSI escape sequences from ABC outputClifford Wolf2014-08-131-0/+15
* | New interface for $__alu in techmap.vClifford Wolf2014-08-131-129/+62
* | Added support for non-standard """ macro bodiesClifford Wolf2014-08-132-1/+21
* | Fixed handling of constant-true branches in proc_cleanClifford Wolf2014-08-122-2/+3
* | Added test_verific mode to tests/fsm/generate.pyClifford Wolf2014-08-121-7/+17
* | Fixed SigBit(RTLIL::Wire *wire) constructorClifford Wolf2014-08-121-1/+1
* | Fixed building verific bindingsClifford Wolf2014-08-122-3/+3
* | Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-121-0/+11
* | Another build fix by americanrouter (via reddit)Clifford Wolf2014-08-111-0/+3
* | Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-102-8/+43
* | Fixed "share" for complex scenarios with never-active cellsClifford Wolf2014-08-091-6/+22
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