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* Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-113-11/+14
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* Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into ↵Eddie Hung2019-06-111-15/+10
| | | | | | | xc7mux" This reverts commit 5174082208ef9bea22ad1ba62622947375b3e83b, reversing changes made to 54379f9872ba3abdf5328994abcf5abfc7288c6b.
* Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7muxEddie Hung2019-06-111-10/+15
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| * Try way that doesn't involve creating a new wireEddie Hung2019-06-111-10/+15
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* | Disable dist RAM boxes due to comb loopEddie Hung2019-06-111-2/+2
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* | Remove #ifndef ABCEddie Hung2019-06-111-4/+0
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* | Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7muxEddie Hung2019-06-103-3/+59
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| * If d_bit already in sigbit_chain_next, create extra wireEddie Hung2019-06-101-3/+6
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| * Add testEddie Hung2019-06-102-0/+53
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* | Revert "Revert "Move ff_map back after ABC for shregmap""Eddie Hung2019-06-101-5/+5
| | | | | | | | This reverts commit e473e7456545d702c011ee7872956f94a8522865.
* | Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"Eddie Hung2019-06-102-6/+6
| | | | | | | | This reverts commit 94a5f4e60985fc1e3fea75eec85638fa29874bea.
* | Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"Eddie Hung2019-06-101-26/+6
| | | | | | | | This reverts commit 45d1bdf83ae6d51628e917b66f1b6043c8a3baee.
* | Revert "Refactor to ShregmapTechXilinx7Static"Eddie Hung2019-06-101-86/+46
| | | | | | | | This reverts commit e1e37db86073e545269ff440da77f57135e8b155.
* | Revert "Add -tech xilinx_static"Eddie Hung2019-06-101-13/+2
| | | | | | | | This reverts commit dfe9d95579ab98d7518d40e427af858243de4eb3.
* | Revert "Continue support for ShregmapTechXilinx7Static"Eddie Hung2019-06-101-81/+30
| | | | | | | | This reverts commit 72eda94a66c8c4938a713c9ae49d560e6b33574f.
* | Revert "shregmap -tech xilinx_static to handle INIT"Eddie Hung2019-06-101-32/+22
| | | | | | | | This reverts commit 935df3569b4677ac38041ff01a2f67185681f4e3.
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-102-1/+30
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| * Add some more commentsEddie Hung2019-06-101-1/+6
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| * Merge pull request #1082 from corecode/u4kDavid Shah2019-06-101-0/+24
| |\ | | | | | | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
| | * ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4kSimon Schubert2019-06-101-0/+24
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| * Merge pull request #1078 from YosysHQ/eddie/muxcover_costsClifford Wolf2019-06-081-12/+42
| |\ | | | | | | Allow muxcover costs to be changed
| | * Allow muxcover costs to be changedEddie Hung2019-06-071-12/+42
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* | | Update CHANGELOGEddie Hung2019-06-071-4/+2
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* | | Comment out muxpack (currently broken)Eddie Hung2019-06-071-2/+2
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* | | Fine tune aigerparseEddie Hung2019-06-072-63/+32
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-0739-867/+1079
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| * | Fix spacing from spaces to tabsEddie Hung2019-06-071-362/+362
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| * | Merge pull request #1079 from YosysHQ/eddie/fix_read_aigerClifford Wolf2019-06-0727-45/+128
| |\ \ | | | | | | | | Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
| | * | Add read_aiger to CHANGELOGEddie Hung2019-06-071-0/+1
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| | * | Fix spacing (entire file is wrong anyway, will fix later)Eddie Hung2019-06-071-3/+3
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| | * | Remove unnecessary std::getline() for ASCIIEddie Hung2019-06-071-3/+0
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| | * | Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
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| | * | Fix read_aiger -- create zero driver, fix init width, parse 'b'Eddie Hung2019-06-072-13/+52
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| | * | Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
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| | * | Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
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| | * | Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
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| * | Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-079-3/+93
| |\ \ | | | | | | | | elaboration system tasks
| | * | Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-074-50/+38
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-0710-5/+107
| | |\ \ | | | | | | | | | | | | | | | clifford/pr983
| | | * | Initial implementation of elaboration system tasksUdi Finkelstein2019-05-0310-5/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
| * | | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
| |/ / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge branch 'tux3-implicit_named_connection'Clifford Wolf2019-06-074-3/+40
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| | * | | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-073-13/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-075-4/+52
| | |\ \ \ | | | |_|/ | | |/| | | | | | | into tux3-implicit_named_connection
| | | * | SystemVerilog support for implicit named port connectionstux32019-06-065-12/+59
| | | | | | | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
| * | | | Merge pull request #1076 from thasti/centos7-build-fixClifford Wolf2019-06-071-1/+0
| |\ \ \ \ | | |/ / / | |/| | | Fix pyosys-build on CentOS7
| | * | | remove boost/log/exceptions.hpp from wrapper generatorStefan Biereigel2019-06-071-1/+0
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* | | | Allow muxcover costs to be changedEddie Hung2019-06-071-12/+42
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* | | | $__XILINX_MUX_ -> $__XILINX_SHIFTXEddie Hung2019-06-062-11/+11
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* | | | Fix muxcover and its techmappingEddie Hung2019-06-062-3/+3
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