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* Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816Clifford Wolf2019-02-211-6/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #817 from eddiehung/dff_initEddie Hung2019-02-201-21/+0
|\ | | | | Cleanup #805
| * Remove simple_defparam testsEddie Hung2019-02-201-21/+0
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* | Merge pull request #805 from eddiehung/dff_initEddie Hung2019-02-194-2/+76
|\| | | | | write_verilog to write initial statement for initial flop state
| * Instead of INIT param on cells, use initial statement with hier ref asEddie Hung2019-02-171-18/+13
| | | | | | | | per @cliffordwolf
| * Revert "Add INIT parameter to all ff/latch cells"Eddie Hung2019-02-172-86/+43
| | | | | | | | This reverts commit 742b4e01b498ae2e735d40565f43607d69a015d8.
| * Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-179-100/+345
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* | Merge pull request #811 from ucb-bar/firrtlfixesClifford Wolf2019-02-176-56/+298
|\ \ | | | | | | Update cells supported for verilog to FIRRTL conversion.
| * | Removed unused variables, functions.Jim Lawson2019-02-151-20/+0
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| * | Append (instead of over-writing) EXTRA_FLAGSJim Lawson2019-02-151-1/+1
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| * | Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-155-55/+317
|/ / | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
* | Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
|\ \ | | | | | | write_verilog: correctly emit asynchronous transparent ports
| * | write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760.
* | | Merge pull request #806 from daveshah1/fsm_opt_no_resetClifford Wolf2019-02-121-1/+2
|\ \ \ | | | | | | | | fsm_opt: Fix runtime error for FSMs without a reset state
| * | | fsm_opt: Fix runtime error for FSMs without a reset stateDavid Shah2019-02-071-1/+2
|/ / / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * Cope WIDTH of ff/latch cells is default of zeroEddie Hung2019-02-061-6/+6
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| | * Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
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| | * RefactorEddie Hung2019-02-061-21/+5
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| | * write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
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| | * Add INIT parameter to all ff/latch cellsEddie Hung2019-02-062-43/+86
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| | * Add tests for simple cases using defparamEddie Hung2019-02-061-0/+21
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| | * Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
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| | * Extend testcaseEddie Hung2019-02-061-2/+34
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| | * Add testcaseEddie Hung2019-02-061-0/+10
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* | Add missing blackslash-to-slash convertion to smtio.py (matching ↵Clifford Wolf2019-02-061-1/+1
|/ | | | | | Smt2Worker::get_id() behavior) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #798 from mmicko/masterClifford Wolf2019-01-271-1/+1
|\ | | | | Fixed Anlogic simulation model
| * Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
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* | Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
|\ \ | | | | | | write_verilog: write $tribuf cell as ternary
| * | write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
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* | | Merge branch 'whitequark-write_verilog_keyword'Clifford Wolf2019-01-275-69/+27
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| * | Remove asicworld tests for (unsupported) switch-level modellingClifford Wolf2019-01-274-69/+0
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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* | Merge pull request #796 from whitequark/proc_clean_typoDavid Shah2019-01-251-1/+1
|\ \ | |/ |/| proc_clean: fix critical typo
| * proc_clean: fix critical typo.whitequark2019-01-231-1/+1
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* Merge pull request #793 from whitequark/proc_clean_fix_fully_defClifford Wolf2019-01-191-1/+7
|\ | | | | proc_clean: fix fully def check to consider compare/signal length
| * proc_clean: fix fully def check to consider compare/signal length.whitequark2019-01-181-1/+7
|/ | | | Fixes #790.
* Cleanups in igloo2 example designClifford Wolf2019-01-176-7/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add SF2 IO buffer insertionClifford Wolf2019-01-176-3/+171
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve Igloo2 exampleClifford Wolf2019-01-178-22/+41
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add optional nullstr argument to log_id()Clifford Wolf2019-01-151-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #788 from whitequark/masterClifford Wolf2019-01-151-5/+17
|\ | | | | Document $tribuf and some gates
| * manual: document some gates.whitequark2019-01-141-9/+11
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| * manual: explain $tribuf cell.whitequark2019-01-141-0/+10
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* | Merge pull request #787 from whitequark/flowmap_relaxClifford Wolf2019-01-157-35/+776
|\ \ | |/ |/| flowmap: implement depth relaxation
| * flowmap: clean up terminology.whitequark2019-01-081-17/+18
| | | | | | | | | | | | | | | | | | | | * "map": group gates into LUTs; * "pack": replace gates with LUTs. This is important because we have FlowMap and DF-Map, and currently our messages are ambiguous. Also clean up some other log messages while we're at it.
| * flowmap: implement depth relaxation.whitequark2019-01-087-22/+762
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