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* Added module->portsClifford Wolf2014-08-149-10/+23
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* Refactoring of CellType classClifford Wolf2014-08-143-155/+139
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* RIP $safe_pmuxClifford Wolf2014-08-1416-98/+21
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* Some improvements in FSM mapping and recodingClifford Wolf2014-08-143-9/+18
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* Added "abc -D" for setting delay targetClifford Wolf2014-08-141-5/+18
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* Updated ABC to 4935c2b946deClifford Wolf2014-08-141-1/+1
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* Added techmap support for actual lookahead carry unitClifford Wolf2014-08-131-22/+73
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* Preparations for lookahead ALU support in techmap.vClifford Wolf2014-08-131-28/+92
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* Filter ANSI escape sequences from ABC outputClifford Wolf2014-08-131-0/+15
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* New interface for $__alu in techmap.vClifford Wolf2014-08-131-129/+62
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* Added support for non-standard """ macro bodiesClifford Wolf2014-08-132-1/+21
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* Fixed handling of constant-true branches in proc_cleanClifford Wolf2014-08-122-2/+3
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* Added test_verific mode to tests/fsm/generate.pyClifford Wolf2014-08-121-7/+17
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* Fixed SigBit(RTLIL::Wire *wire) constructorClifford Wolf2014-08-121-1/+1
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* Fixed building verific bindingsClifford Wolf2014-08-122-3/+3
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* Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-121-0/+11
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* Another build fix by americanrouter (via reddit)Clifford Wolf2014-08-111-0/+3
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* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-102-8/+43
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* Fixed "share" for complex scenarios with never-active cellsClifford Wolf2014-08-091-6/+22
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* Do not share any $reduce_* cells (its complicated and not worth it anyways)Clifford Wolf2014-08-091-19/+0
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* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-093-51/+103
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* Improved FSM testsClifford Wolf2014-08-084-2/+5
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* Another fsm_extract bugfixClifford Wolf2014-08-081-0/+4
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* Fixed "fsm -export"Clifford Wolf2014-08-082-6/+5
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* Fixed sharing of reduce operatorClifford Wolf2014-08-081-0/+13
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* Fixed fsm_extract for wreduced muxesClifford Wolf2014-08-081-8/+25
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* Added FSM test benchClifford Wolf2014-08-082-0/+113
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* Added "sat -prove-skip"Clifford Wolf2014-08-081-2/+16
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* Fixed build with gcc-4.6Clifford Wolf2014-08-076-16/+24
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* Use "-keepdc" in "miter -equiv -flatten"Clifford Wolf2014-08-071-2/+2
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* Also allow "module foobar(input foo, output bar, ...);" syntaxClifford Wolf2014-08-071-3/+5
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* Added adff2dff.v (for techmap -share_map)Clifford Wolf2014-08-072-1/+32
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* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-065-6/+80
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* Various improvements in memory_dff passClifford Wolf2014-08-061-21/+22
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* Various fixes and improvements in wreduce passClifford Wolf2014-08-051-29/+47
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* Removed old "constmap" from wreduce codeClifford Wolf2014-08-051-3/+2
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* Added support for truncating of wires to wreduce passClifford Wolf2014-08-054-12/+93
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* Cleanups and improvements in wreduce passClifford Wolf2014-08-051-47/+77
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* Added mux support to wreduce commandClifford Wolf2014-08-051-36/+82
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* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-054-9/+90
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* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-052-3/+16
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* Added "show -signed"Clifford Wolf2014-08-041-5/+17
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* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-042-1/+12
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* Added RTLIL::IdString::in(...)Clifford Wolf2014-08-042-9/+21
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* Fixed "share" for memory read portsClifford Wolf2014-08-031-0/+7
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* Added "wreduce" to some of the standard test benchesClifford Wolf2014-08-033-2/+3
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* Progress in "wreduce" passClifford Wolf2014-08-031-43/+16
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* Added "wreduce" command (work in progress)Clifford Wolf2014-08-032-0/+253
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* Added query() API to ModIndexClifford Wolf2014-08-031-8/+46
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* Added ID() macro for static IdStringsClifford Wolf2014-08-031-0/+3
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