iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Support PRIM_BUFIF1 primitive	Miodrag Milanovic	2021-10-14	1	-2/+2
*	Bump version	github-actions[bot]	2021-10-12	1	-1/+1
*	Merge pull request #3039 from YosysHQ/claire/verific_aldff	Claire Xen	2021-10-11	2	-1/+91
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\| *	Add Verific adffe/dffsre/aldffe FIXMEs	Claire Xenia Wolf	2021-10-11	1	-0/+3
\| *	Fixes and add comments for open FIXME items	Claire Xenia Wolf	2021-10-08	1	-1/+34
\| *	Add support for $aldff flip-flops to verific importer	Claire Xenia Wolf	2021-10-08	2	-1/+55
* \|	Merge pull request #3040 from YosysHQ/micko/split_module_ports	Claire Xen	2021-10-11	1	-0/+2
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\| * \|	Split module ports, 20 per line	Miodrag Milanovic	2021-10-09	1	-0/+2
* \| \|	Merge pull request #3041 from YosysHQ/mmicko/module_attr	Claire Xen	2021-10-11	1	-0/+1
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\| * \|	Import module attributes from Verific	Miodrag Milanovic	2021-10-10	1	-0/+1
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* \|	Bump version	github-actions[bot]	2021-10-09	1	-1/+1
* \|	Fix a regression from #3035.	Marcelina Kościelnicka	2021-10-08	2	-1/+22
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*	Bump version	github-actions[bot]	2021-10-08	1	-1/+1
*	FfData: some refactoring.	Marcelina Kościelnicka	2021-10-07	14	-546/+660
*	Bump version	github-actions[bot]	2021-10-05	1	-1/+1
*	verific set db_infer_set_reset_registers	Miodrag Milanovic	2021-10-04	1	-0/+1
*	Bump version	github-actions[bot]	2021-10-03	1	-1/+1
*	Hook up $aldff support in various passes.	Marcelina Kościelnicka	2021-10-02	9	-11/+77
*	zinit: Refactor to use FfData.	Marcelina Kościelnicka	2021-10-02	1	-101/+38
*	kernel/ff: Refactor FfData to enable FFs with async load.	Marcelina Kościelnicka	2021-10-02	10	-325/+565
*	Add $aldff and $aldffe: flip-flops with async load.	Marcelina Kościelnicka	2021-10-02	9	-2/+527
*	Specify minimum bison version 3.0+	Zachary Snow	2021-10-01	2	-0/+4
*	simplemap: refactor to use FfData.	Marcelina Kościelnicka	2021-10-02	3	-290/+26
*	Merge pull request #3017 from YosysHQ/claire/short_rtlil_x_const	Miodrag Milanović	2021-09-28	1	-9/+13
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\| *	Add optimization to rtlil back-end for all-x parameter values	Claire Xenia Wolf	2021-09-27	1	-9/+13
* \|	Bump version	github-actions[bot]	2021-09-28	1	-1/+1
* \|	Prepare for next release cycle	Miodrag Milanovic	2021-09-27	2	-3/+6
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*	Bump version	github-actions[bot]	2021-09-25	1	-1/+1
*	Merge pull request #3014 from YosysHQ/claire/fix-vgtest	Claire Xen	2021-09-24	41	-79/+80
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\| *	Fix TOK_ID memory leak in for_initialization	Zachary Snow	2021-09-23	1	-0/+1
\| *	Fix "make vgtest" so it runs to the end (but now it fails ;)	Claire Xenia Wolf	2021-09-23	40	-79/+79
* \|	Bump version	github-actions[bot]	2021-09-22	1	-1/+1
* \|	sv: support wand and wor of data types	Zachary Snow	2021-09-21	4	-10/+53
* \|	verilog: fix multiple AST_PREFIX scope resolution issues	Zachary Snow	2021-09-21	4	-4/+110
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*	Bump version	github-actions[bot]	2021-09-19	1	-1/+1
*	Merge pull request #3010 from the6p4c/master	Miodrag Milanović	2021-09-18	1	-0/+2
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\| *	Fix protobuf backend build dependencies	the6p4c	2021-09-17	1	-0/+2
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*	Bump version	github-actions[bot]	2021-09-14	1	-1/+1
*	verilog: Squash flex-triggered warning.	Marcelina Kościelnicka	2021-09-13	1	-0/+2
*	Updates for CHANGELOG (#2997)	Miodrag Milanović	2021-09-13	1	-48/+126
*	Bump version	github-actions[bot]	2021-09-11	1	-1/+1
*	Merge pull request #3001 from YosysHQ/claire/sigcheck	Miodrag Milanović	2021-09-10	2	-6/+14
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\| *	Add additional check to SigSpec	Claire Xenia Wolf	2021-09-10	2	-6/+14
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*	yosys-smtbmc: Fix reused loop variable.	Marcelina Kościelnicka	2021-09-10	1	-4/+4
*	Bump version	github-actions[bot]	2021-09-10	1	-1/+1
*	abc9: make re-entrant (#2993)	Eddie Hung	2021-09-09	3	-9/+29
*	abc9: holes module to instantiate cells with NEW_ID (#2992)	Eddie Hung	2021-09-09	2	-1/+15
*	abc9: replace cell type/parameters if derived type already processed (#2991)	Eddie Hung	2021-09-09	3	-7/+30
*	Bump version	github-actions[bot]	2021-09-03	1	-1/+1
*	update required verific version	Miodrag Milanovic	2021-09-02	1	-1/+1