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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CIs before PIs; also sort each cell's connections before iteratingEddie Hung2019-04-161-5/+7
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-161-28/+0
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #939 from YosysHQ/revert895Eddie Hung2019-04-161-28/+0
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert #895 (mux-to-shiftx optimisation)
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert #895Eddie Hung2019-04-161-28/+0
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | / / / Port from xc7mux branchEddie Hung2019-04-163-54/+167
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-enable partsel.v testEddie Hung2019-04-161-1/+0
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | abc9 to call "setundef -zero" behaving as for abcEddie Hung2019-04-161-0/+3
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-153-6/+5
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatchEddie Hung2019-04-152-4/+3
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert "Recognise default entry in case even if all cases covered (fix for #931)"
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert "Recognise default entry in case even if all cases covered (fix for ↵Eddie Hung2019-04-152-4/+3
| |/ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | #931)"
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #936 from YosysHQ/README-fix-quotesEddie Hung2019-04-151-2/+2
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|/ / / / / / / / / / / / / / / / / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | README: fix some incorrect quoting
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | README: fix some incorrect quoting.whitequark2019-04-151-2/+2
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Forgot backslashesEddie Hung2019-04-121-1/+1
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Handle __dummy_o__ and __const[01]__ in read_aiger not abcEddie Hung2019-04-122-18/+8
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | abc to ignore __dummy_o__ and __const[01]__ when re-integratingEddie Hung2019-04-121-6/+20
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Output __const0__ and __const1__ CIsEddie Hung2019-04-121-7/+10
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-121-12/+32
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix inout handling for -map optionEddie Hung2019-04-121-10/+30
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-120-0/+0
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-127-50/+76
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use -map instead of -symbols for aigerEddie Hung2019-04-121-2/+3
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ci_bits and co_bits now a list, order is important for ABCEddie Hung2019-04-121-24/+34
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also cope with duplicated CIsEddie Hung2019-04-121-5/+23
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WIPEddie Hung2019-04-121-14/+68
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Comment outEddie Hung2019-04-121-1/+1
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-122-1/+14
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cope with an output having same name as an input (i.e. CO)Eddie Hung2019-04-121-5/+23
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* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-127-50/+76
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Add additional cells sim models for core 7-series primitives.
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
| | | |/ / / / / / / / / / / / / / / / / / / / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #933 from dh73/masterClifford Wolf2019-04-121-3/+9
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixing issues in CycloneV cell sim
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #932 from YosysHQ/eddie/fixdlatchClifford Wolf2019-04-122-3/+4
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |/ / / / / / / / / / / / / / / / / / / / / / / / / / | |/| | | | | | | | | | | | | / / / / / / / / / / / / / | | | |_|_|_|_|_|_|_|_|_|_|_|/ / / / / / / / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | Recognise default entry in case even if all cases covered (fix for #931)
| | * | | | | | | | | | | | | | | | | | | | | | | | | Add default entry to testcaseEddie Hung2019-04-111-2/+3
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Recognise default entry in case even if all cases covered (#931)Eddie Hung2019-04-111-1/+1
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| * | | | | | | | | | | | | | | | | | | | | | | | | Fix a few typosEddie Hung2019-04-081-3/+3
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* | | | | | | | | | | | | | | | | | | | | | | | | | Add non-input bits driven by unrecognised cells as ci_bitsEddie Hung2019-04-101-1/+1
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* | | | | | | | | | | | | | | | | | | | | | | | | parse_aiger() to rename all $lut cells after "clean"Eddie Hung2019-04-101-24/+21
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* | | | | | | | | | | | | | | | | | | | | | | | More space fixingEddie Hung2019-04-081-2/+2
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* | | | | | | | | | | | | | | | | | | | | | | | Fix spacingEddie Hung2019-04-081-29/+29
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* | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'master' into xaigEddie Hung2019-04-08115-710/+5842
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| * | | | | | | | | | | | | | | | | | | | | | | Merge pull request #919 from YosysHQ/multiport_transpClifford Wolf2019-04-081-1/+2
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |/ / / / / / / / / / / / / / / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | memory_bram: Fix multiport make_transp
| | * | | | | | | | | | | | | | | | | | | | | | memory_bram: Fix multiport make_transpDavid Shah2019-04-071-1/+2
| |/ / / / / / / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | | | | | | Add "read_ilang -lib"Clifford Wolf2019-04-055-3/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | | | | | Added missing argument checking to "mutate" commandClifford Wolf2019-04-041-0/+32
| | |_|/ / / / / / / / / / / / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | | | | Merge pull request #913 from smunaut/fix_proc_muxEddie Hung2019-04-031-1/+1
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|_|_|_|/ / / / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
| | * | | | | | | | | | | | | | | | | | | | proc_mux: Fix crash when trying to optimize non-existant mux to shiftxSylvain Munaut2019-04-031-1/+1
| |/ / / / / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | last_mux_cell can be NULL ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | | | | | | | | | | | | | | | | | | | Merge pull request #912 from YosysHQ/bram_addr_enClifford Wolf2019-04-031-0/+2
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | memory_bram: Consider read enable for address expansion register
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-24 06:13:54 +0000