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* Added memory_memx pass, "memory -memx", and "prep -memx"Clifford Wolf2016-08-194-4/+121
* Optimize memory address port width in wreduce and memory_collect, not verilog...Clifford Wolf2016-08-194-7/+44
* Added missing support for mem read enable ports to verilog back-endClifford Wolf2016-08-181-6/+14
* Bugfix in test_autotbClifford Wolf2016-08-181-0/+4
* Improved smtbmc vcd generation performanceClifford Wolf2016-08-182-20/+40
* Added printing of code loc of failed asserts to yosys-smtbmcClifford Wolf2016-08-173-1/+23
* Fixed default build configClifford Wolf2016-08-161-1/+2
* Merge pull request #203 from cr1901/masterClifford Wolf2016-08-162-4/+17
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| * Add MSYS2-compatible build.William D. Jones2016-08-162-4/+17
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* Use _Exit(0) on win32, always use _Exit(1) in log_error()Clifford Wolf2016-08-162-1/+6
* Updated ABC to hg rev a86455b00da5Clifford Wolf2016-08-161-1/+1
* Fixed use-after-free dict<> usage pattern in hierarchy.ccClifford Wolf2016-08-161-1/+3
* Updated ABC to hg rev 760ba358e790Clifford Wolf2016-08-161-1/+1
* ABC mxe cross-build fixClifford Wolf2016-08-161-1/+1
* Minor fixes in show commandClifford Wolf2016-08-161-3/+3
* Added greenpak4_dffinvClifford Wolf2016-08-153-0/+199
* Fixed upto handling in verilog back-endClifford Wolf2016-08-151-0/+3
* Merge pull request #200 from azonenberg/masterClifford Wolf2016-08-142-10/+78
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| * greenpak4: Changed name of inverted output ports for consistencyAndrew Zonenberg2016-08-142-19/+19
| * greenpak4: Added GP_DFFxI cellsAndrew Zonenberg2016-08-142-0/+68
| * greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)Andrew Zonenberg2016-08-131-10/+10
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* Merge pull request #198 from whitequark/masterClifford Wolf2016-08-111-0/+2
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| * synth_greenpak4: use attrmvcp to move LOC from wires to cells.whitequark2016-08-101-0/+2
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* Only allow posedge/negedge with 1 bit wide signalsClifford Wolf2016-08-101-0/+2
* Fixed some compiler warnings in attrmap commandClifford Wolf2016-08-101-4/+4
* Added "attrmap" commandClifford Wolf2016-08-093-0/+253
* Added log_const() APIClifford Wolf2016-08-092-0/+19
* Added "attrmvcp" passClifford Wolf2016-08-092-0/+138
* Use /proc/self/exe on Cygwin as well.Yury Gribov2016-08-081-1/+1
* Undo "preserve wire attributes in iopadmap" change (it was OK before)Clifford Wolf2016-08-081-1/+1
* Added "test_autotb -seed" (and "autotest.sh -S")Clifford Wolf2016-08-062-5/+12
* preserve wire attributes in iopadmapClifford Wolf2016-08-061-1/+1
* Fixed bug in parsing real constantsClifford Wolf2016-08-061-4/+4
* Added "insbuf" commandClifford Wolf2016-08-022-0/+95
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-07-3016-22/+162
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| * Added $initstate support to smtbmc flowClifford Wolf2016-07-273-2/+19
| * Added SatGen support for $anyconstClifford Wolf2016-07-271-0/+22
| * Removed $predict support from SatGenClifford Wolf2016-07-271-9/+0
| * Added $anyconst and $aconstClifford Wolf2016-07-277-2/+83
| * Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-275-9/+38
* | Added "write_verilog -defparam"Clifford Wolf2016-07-301-2/+21
* | Added "write_verilog -nodec -nostr"Clifford Wolf2016-07-301-4/+27
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* Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()Clifford Wolf2016-07-253-3/+3
* Fixed a verilog parser memory leakClifford Wolf2016-07-251-0/+1
* Fixed parsing of empty positional cell portsClifford Wolf2016-07-251-2/+31
* Improvements in CellEdgesDatabaseClifford Wolf2016-07-243-16/+167
* Added CellEdgesDatabase APIClifford Wolf2016-07-244-1/+250
* Moved SatHelper::setup_init() code to SatHelper::setup()Clifford Wolf2016-07-241-97/+92
* Added $initstate support to "sat" commandClifford Wolf2016-07-231-13/+12
* No tristate warning message for "read_verilog -lib"Clifford Wolf2016-07-233-8/+11
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