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* preserve wire attributes in iopadmapClifford Wolf2016-08-061-1/+1
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* Fixed bug in parsing real constantsClifford Wolf2016-08-061-4/+4
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* Added "insbuf" commandClifford Wolf2016-08-022-0/+95
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-07-3016-22/+162
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| * Added $initstate support to smtbmc flowClifford Wolf2016-07-273-2/+19
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| * Added SatGen support for $anyconstClifford Wolf2016-07-271-0/+22
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| * Removed $predict support from SatGenClifford Wolf2016-07-271-9/+0
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| * Added $anyconst and $aconstClifford Wolf2016-07-277-2/+83
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| * Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-275-9/+38
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* | Added "write_verilog -defparam"Clifford Wolf2016-07-301-2/+21
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* | Added "write_verilog -nodec -nostr"Clifford Wolf2016-07-301-4/+27
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* Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()Clifford Wolf2016-07-253-3/+3
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* Fixed a verilog parser memory leakClifford Wolf2016-07-251-0/+1
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* Fixed parsing of empty positional cell portsClifford Wolf2016-07-251-2/+31
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* Improvements in CellEdgesDatabaseClifford Wolf2016-07-243-16/+167
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* Added CellEdgesDatabase APIClifford Wolf2016-07-244-1/+250
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* Moved SatHelper::setup_init() code to SatHelper::setup()Clifford Wolf2016-07-241-97/+92
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* Added $initstate support to "sat" commandClifford Wolf2016-07-231-13/+12
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* No tristate warning message for "read_verilog -lib"Clifford Wolf2016-07-233-8/+11
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* Added satgen initstate supportClifford Wolf2016-07-221-0/+27
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* Using $initstate in "initial assume" and "initial assert"Clifford Wolf2016-07-211-1/+6
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* Added $initstate cell type and vlog functionClifford Wolf2016-07-217-4/+54
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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-2116-32/+28
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* Added basic support for $expect cellsClifford Wolf2016-07-1316-19/+82
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* Added examples/smtbmcClifford Wolf2016-07-132-0/+30
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* Merge pull request #191 from whitequark/json-module-attributesClifford Wolf2016-07-131-2/+6
|\ | | | | write_json: also write module attributes
| * write_json: also write module attributes.whitequark2016-07-121-2/+6
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* | Merge pull request #193 from azonenberg/masterClifford Wolf2016-07-132-2/+9
|\ \ | | | | | | Removed splitnets in synth_greenpak4, added GP_DAC, refactored GP_BANDGAP
| * \ Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-07-121-2/+5
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* | | Minor bugfix in FSM reset state detectionClifford Wolf2016-07-121-2/+5
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| * Added GP_DAC cellAndrew Zonenberg2016-07-111-0/+8
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| * Removed VOUT port of GP_BANDGAPAndrew Zonenberg2016-07-111-1/+1
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| * Removed splitnets in prep for new gp4par parserAndrew Zonenberg2016-07-111-1/+0
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* Yosys-smtbmc: Support for hierarchical VCD dumpingClifford Wolf2016-07-112-23/+59
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* Moved smt2 yosys info parsing from smtbmc.py to smtio.pyClifford Wolf2016-07-113-16/+56
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* Added "prep -auto-top" and "synth -auto-top"Clifford Wolf2016-07-112-6/+23
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-07-101-0/+26
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| * Merge pull request #189 from whitequark/masterClifford Wolf2016-07-101-0/+26
| |\ | | | | | | greenpak4: add GP_COUNT{8,14}_ADV cells
| | * greenpak4: add GP_COUNT{8,14}_ADV cells.whitequark2016-07-101-0/+26
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* / Support for hierarchical designs in smt2 back-endClifford Wolf2016-07-102-24/+144
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* Further improved fsm_detect output, attempt to detect self-resetting circuitsClifford Wolf2016-07-091-6/+68
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* Added printing of some warning messages to fsm_detectClifford Wolf2016-07-091-14/+61
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* Added warning about adding fsm_encoding attributes to wires to manualClifford Wolf2016-07-081-0/+4
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* Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiationsClifford Wolf2016-07-082-13/+24
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* Fixed mem assignment in left-hand-side concatenationClifford Wolf2016-07-082-0/+57
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* Merge branch 'eddiehung-vtr'Clifford Wolf2016-07-081-9/+17
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| * Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behaviorClifford Wolf2016-07-081-13/+15
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| * In BLIF, a .names without entries already always outputs 0Clifford Wolf2016-07-081-11/+0
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| * Undo eddiehung-vtr Makefile changesClifford Wolf2016-07-081-5/+1
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| * Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into ↵Clifford Wolf2016-07-082-3/+24
|/| | | | | | | eddiehung-vtr
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