| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Connections between inputs and inouts are driven by the input | Clifford Wolf | 2016-04-26 | 1 | -0/+3 |
| * | Fixed test_autotb for modules with many cell ports | Clifford Wolf | 2016-04-25 | 1 | -3/+6 |
| * | Fixed proc_mux performance bug | Clifford Wolf | 2016-04-25 | 1 | -0/+3 |
| * | Merge pull request #150 from azonenberg/master | Clifford Wolf | 2016-04-25 | 1 | -0/+13 |
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| | * | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-04-24 | 6 | -72/+163 |
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| * | | Fixed performance bug in proc_dlatch | Clifford Wolf | 2016-04-24 | 1 | -2/+61 |
| * | | Added "yosys -D ALL" | Clifford Wolf | 2016-04-24 | 3 | -6/+22 |
| * | | Added "prep -flatten" and "synth -flatten" | Clifford Wolf | 2016-04-24 | 2 | -7/+36 |
| * | | Converted "prep" to ScriptPass | Clifford Wolf | 2016-04-24 | 2 | -60/+47 |
| | * | Removed VIN_BUF_EN | Andrew Zonenberg | 2016-04-24 | 1 | -1/+0 |
| | * | Renamed VOUT to OUT on GP_ACMP cell | Andrew Zonenberg | 2016-04-23 | 1 | -1/+3 |
| | * | Added GP_ACMP cell | Andrew Zonenberg | 2016-04-23 | 1 | -0/+12 |
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| * | Improvements in greenpak4 shreg mapping | Clifford Wolf | 2016-04-23 | 1 | -16/+35 |
| * | Run clean after splitnets in synth_greenpak4 | Clifford Wolf | 2016-04-23 | 1 | -1/+1 |
| * | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-04-23 | 1 | -0/+1 |
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| | * | Added "shregmap -zinit" for greenpak4 tech | Clifford Wolf | 2016-04-23 | 1 | -0/+1 |
| * | | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-04-23 | 2 | -111/+72 |
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| | * | Merge https://github.com/azonenberg/yosys | Clifford Wolf | 2016-04-23 | 1 | -1/+7 |
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| | * | | Added "shregmap" to synth_greenpak4 | Clifford Wolf | 2016-04-23 | 1 | -0/+1 |
| | * | | Converted synth_greenpak4 to ScriptPass | Clifford Wolf | 2016-04-23 | 2 | -111/+71 |
| * | | | Fixed typo in help text | Andrew Zonenberg | 2016-04-22 | 1 | -1/+1 |
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| * | | Fixed typo | Andrew Zonenberg | 2016-04-22 | 1 | -1/+1 |
| * | | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-04-22 | 118 | -202/+497 |
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| | * | Added "shregmap -tech greenpak4" | Clifford Wolf | 2016-04-22 | 1 | -6/+97 |
| | * | Added support for "active high" and "active low" latches in BLIF front-end | Clifford Wolf | 2016-04-22 | 1 | -0/+4 |
| | * | Added support for "active high" and "active low" latches in BLIF back-end | Clifford Wolf | 2016-04-22 | 1 | -0/+12 |
| | * | More flexible handling of initialization values | Clifford Wolf | 2016-04-22 | 1 | -7/+22 |
| | * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 113 | -145/+172 |
| | * | Fixed performance bug in "share" pass | Clifford Wolf | 2016-04-21 | 1 | -2/+51 |
| | * | Fixed handling of parameters and const functions in casex/casez pattern | Clifford Wolf | 2016-04-21 | 5 | -8/+37 |
| | * | Improvements in opt_expr | Clifford Wolf | 2016-04-21 | 1 | -12/+62 |
| | * | Bugfix and improvements in memory_share | Clifford Wolf | 2016-04-21 | 2 | -22/+40 |
| * | | Added GP_VREF cell | Andrew Zonenberg | 2016-04-20 | 1 | -0/+6 |
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| * | Merge pull request #149 from azonenberg/master | Clifford Wolf | 2016-04-19 | 1 | -96/+156 |
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| | * | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-04-18 | 1 | -5/+107 |
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| * | | Added "shregmap -params" | Clifford Wolf | 2016-04-18 | 1 | -4/+43 |
| * | | Added "shregmap -zinit" and "shregmap -init" | Clifford Wolf | 2016-04-18 | 1 | -2/+65 |
| | * | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-04-17 | 1 | -30/+140 |
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| * | | Improvements in "shregmap" | Clifford Wolf | 2016-04-17 | 1 | -30/+140 |
| | * | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-04-16 | 4 | -2/+264 |
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| * | | Added "shregmap" pass | Clifford Wolf | 2016-04-16 | 2 | -0/+262 |
| * | | Fixed copy&paste error in log message in lut2mux | Clifford Wolf | 2016-04-16 | 1 | -1/+1 |
| * | | Minor hashlib bugfix | Clifford Wolf | 2016-04-16 | 1 | -1/+1 |
| | * | Added GP_SHREG cell | Andrew Zonenberg | 2016-04-13 | 1 | -0/+23 |
| | * | Refactoring: alphabetized cells_sim | Andrew Zonenberg | 2016-04-13 | 1 | -120/+119 |
| | * | Fixed missing semicolon | Andrew Zonenberg | 2016-04-09 | 1 | -1/+1 |
| | * | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-04-09 | 0 | -0/+0 |
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| * | | Merge pull request #147 from azonenberg/master | Clifford Wolf | 2016-04-08 | 2 | -4/+70 |
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| | | * | Added GP_RCOSC cell | Andrew Zonenberg | 2016-04-09 | 1 | -0/+38 |
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| | * | Fixed assertion failure for non-inferrable counters in some cases | Andrew Zonenberg | 2016-04-06 | 1 | -2/+6 |
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index : iCE40/yosys | |
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