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authorAndrew Zonenberg <azonenberg@drawersteak.com>2016-04-13 23:13:51 -0700
committerAndrew Zonenberg <azonenberg@drawersteak.com>2016-04-13 23:13:51 -0700
commitd0aaf8d2621fd75b968700ec4cb8dd6acf568737 (patch)
tree24596bd3c0122a2c1d7735aa99b0dba1c2cccb6d
parentcdefa60367cf15b2e0a7fb35e4a42fe8358755b5 (diff)
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Added GP_SHREG cell
-rw-r--r--techlibs/greenpak4/cells_sim.v23
1 files changed, 23 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 1860970d2..554e2e13f 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -227,6 +227,29 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRI
endmodule
+module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
+
+ parameter OUTA_DELAY = 1;
+ parameter OUTA_INVERT = 0;
+ parameter OUTB_DELAY = 1;
+
+ reg[15:0] shreg = 0;
+
+ always @(posedge clk, negedge RSTN) begin
+
+ if(!nRST)
+ shreg = 0;
+
+ else
+ shreg <= {shreg[14:0], IN};
+
+ end
+
+ assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
+ assign OUTB = shreg[OUTB_DELAY - 1];
+
+endmodule
+
//keep constraint needed to prevent optimization since we have no outputs
(* keep *)
module GP_SYSRESET(input RST);