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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-06 23:42:22 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-06 23:42:22 -0700 |
| commit | 01a5f711871658c9997f7352414cd4ac50ed772c (patch) | |
| tree | 3f51eed7a79e513e2ad632cfcd2989654b150523 | |
| parent | 48c10d90f4b8c813782d4c5a304b2e1e24d140d8 (diff) | |
| download | yosys-01a5f711871658c9997f7352414cd4ac50ed772c.tar.gz yosys-01a5f711871658c9997f7352414cd4ac50ed772c.tar.bz2 yosys-01a5f711871658c9997f7352414cd4ac50ed772c.zip | |
Fixed assertion failure for non-inferrable counters in some cases
| -rw-r--r-- | techlibs/greenpak4/greenpak4_counters.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/greenpak4/greenpak4_counters.cc b/techlibs/greenpak4/greenpak4_counters.cc index 394f3dab1..7b5646bf2 100644 --- a/techlibs/greenpak4/greenpak4_counters.cc +++ b/techlibs/greenpak4/greenpak4_counters.cc @@ -248,8 +248,12 @@ void greenpak4_counters_worker( if (cell->type != "$alu") return; - //A input is the count value. Check if it has COUNT_EXTRACT set - RTLIL::Wire* a_wire = sigmap(cell->getPort("\\A")).as_wire(); + //A input is the count value. Check if it has COUNT_EXTRACT set. + //If it's not a wire, don't even try + auto port = sigmap(cell->getPort("\\A")); + if(!port.is_wire()) + return; + RTLIL::Wire* a_wire = port.as_wire(); bool force_extract = false; bool never_extract = false; string count_reg_src = a_wire->attributes["\\src"].decode_string().c_str(); |