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author | Clifford Wolf <clifford@clifford.at> | 2016-04-08 11:58:40 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-04-08 11:58:40 +0200 |
commit | 3d9ff912c208d330fea12c0149fbe352e9ea7c0a (patch) | |
tree | 3f51eed7a79e513e2ad632cfcd2989654b150523 | |
parent | ace462237f1223a41f6d29d1fe29652fcf435882 (diff) | |
parent | 01a5f711871658c9997f7352414cd4ac50ed772c (diff) | |
download | yosys-3d9ff912c208d330fea12c0149fbe352e9ea7c0a.tar.gz yosys-3d9ff912c208d330fea12c0149fbe352e9ea7c0a.tar.bz2 yosys-3d9ff912c208d330fea12c0149fbe352e9ea7c0a.zip |
Merge pull request #147 from azonenberg/master
Added GP_BANDGAP, GP_POR, GP_RINGOSC primitives
-rw-r--r-- | techlibs/greenpak4/cells_sim.v | 66 | ||||
-rw-r--r-- | techlibs/greenpak4/greenpak4_counters.cc | 8 |
2 files changed, 70 insertions, 4 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 4ea576960..1234ce1b2 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -75,13 +75,44 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT); initial CLKOUT = 0; + //auto powerdown not implemented for simulation + //output dividers not implemented for simulation + always begin if(PWRDN) - clkout = 0; + CLKOUT = 0; else begin //half period of 1730 Hz #289017; - clkout = ~clkout; + CLKOUT = ~CLKOUT; + end + end + +endmodule + +module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC); + + parameter PWRDN_EN = 0; + parameter AUTO_PWRDN = 0; + parameter PRE_DIV = 1; + parameter FABRIC_DIV = 1; + + initial CLKOUT_PREDIV = 0; + initial CLKOUT_FABRIC = 0; + + //output dividers not implemented for simulation + //auto powerdown not implemented for simulation + + always begin + if(PWRDN) begin + CLKOUT_PREDIV = 0; + CLKOUT_FABRIC = 0; + end + else begin + //half period of 27 MHz + #18.518; + CLKOUT_PREDIV = ~CLKOUT_PREDIV; + CLKOUT_FABRIC = ~CLKOUT_FABRIC; end end @@ -144,3 +175,34 @@ module GP_SYSRESET(input RST); //cannot simulate whole system reset endmodule + +module GP_BANDGAP(output reg OK, output reg VOUT); + parameter AUTO_PWRDN = 1; + parameter CHOPPER_EN = 1; + parameter OUT_DELAY = 100; + + //cannot simulate mixed signal IP + +endmodule + + +module GP_POR(output reg RST_DONE); + parameter POR_TIME = 500; + + initial begin + RST_DONE = 0; + + if(POR_TIME == 4) + #4000; + else if(POR_TIME == 500) + #500000; + else begin + $display("ERROR: bad POR_TIME for GP_POR cell"); + $finish; + end + + RST_DONE = 1; + + end + +endmodule diff --git a/techlibs/greenpak4/greenpak4_counters.cc b/techlibs/greenpak4/greenpak4_counters.cc index 394f3dab1..7b5646bf2 100644 --- a/techlibs/greenpak4/greenpak4_counters.cc +++ b/techlibs/greenpak4/greenpak4_counters.cc @@ -248,8 +248,12 @@ void greenpak4_counters_worker( if (cell->type != "$alu") return; - //A input is the count value. Check if it has COUNT_EXTRACT set - RTLIL::Wire* a_wire = sigmap(cell->getPort("\\A")).as_wire(); + //A input is the count value. Check if it has COUNT_EXTRACT set. + //If it's not a wire, don't even try + auto port = sigmap(cell->getPort("\\A")); + if(!port.is_wire()) + return; + RTLIL::Wire* a_wire = port.as_wire(); bool force_extract = false; bool never_extract = false; string count_reg_src = a_wire->attributes["\\src"].decode_string().c_str(); |