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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-22 18:09:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-08-22 18:09:37 +0200 |
| commit | 151db528e44fd12f3c31561df3bb37c12dca48ad (patch) | |
| tree | 6df49bf7408173207b70d52683c9854d559d9c06 | |
| parent | 2c8c8b3c74ccc630e56c412a83fa60fb7066fb4d (diff) | |
| download | yosys-151db528e44fd12f3c31561df3bb37c12dca48ad.tar.gz yosys-151db528e44fd12f3c31561df3bb37c12dca48ad.tar.bz2 yosys-151db528e44fd12f3c31561df3bb37c12dca48ad.zip | |
Fix missing newline at end of file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | techlibs/anlogic/arith_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v index d783b0212..1186543da 100644 --- a/techlibs/anlogic/arith_map.v +++ b/techlibs/anlogic/arith_map.v @@ -81,4 +81,4 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); /* End implementation */ assign X = AA ^ BB; -endmodule
\ No newline at end of file +endmodule |