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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:34:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:16:54 -0700 |
| commit | e7a8cdbccfa6f619f2e25c540b5af6d8e34ff431 (patch) | |
| tree | 0f9bfe654103f7dc3cafb070b0525647ae0f5b8d | |
| parent | 8691596d19e2384ccf946f2b391bf5c17db0d60e (diff) | |
| download | yosys-e7a8cdbccfa6f619f2e25c540b5af6d8e34ff431.tar.gz yosys-e7a8cdbccfa6f619f2e25c540b5af6d8e34ff431.tar.bz2 yosys-e7a8cdbccfa6f619f2e25c540b5af6d8e34ff431.zip | |
Add shregmap -tech xilinx test
| -rw-r--r-- | tests/various/shregmap.ys | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index 0e5fe882b..a717c54f1 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -64,3 +64,4 @@ sat -verify -prove-asserts -show-ports -seq 5 miter # design -load gate # stat + |