| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix compiler warning in verific.cc | Clifford Wolf | 2018-10-08 | 1 | -0/+2 |
| * | Fix misspelling in issue_template.md | Tim Ansell | 2018-10-08 | 1 | -1/+1 |
| * | Fix IdString M in setup_stdcells() | Adrian Wheeldon | 2018-10-08 | 1 | -1/+1 |
| * | Add inout ports to cells_xtra.v | Clifford Wolf | 2018-10-08 | 2 | -2/+14 |
| * | xilinx: Adding missing inout IO port to IOBUF | Tim Ansell | 2018-10-08 | 1 | -0/+1 |
| * | Fix for issue 594. | Tom Verbeure | 2018-10-08 | 1 | -1/+2 |
| * | Add read_verilog $changed support | Dan Gisselquist | 2018-10-08 | 1 | -1/+4 |
| * | ecp5: Don't map ROMs to DRAM | David Shah | 2018-10-08 | 1 | -0/+1 |
| * | Fix handling of $past 2nd argument in read_verilog | Clifford Wolf | 2018-10-08 | 1 | -1/+1 |
| * | Update to v2 YosysVS template | Clifford Wolf | 2018-10-08 | 1 | -4/+4 |
| * | Add "read_verilog -noassert -noassume -assert-assumes" | Clifford Wolf | 2018-10-08 | 3 | -6/+49 |
| * | Added support for ommited "parameter" in Verilog-2001 style parameter decl in... | Clifford Wolf | 2018-10-08 | 1 | -3/+9 |
| * | Update CHANGELOG | Clifford Wolf | 2018-10-08 | 1 | -2/+35 |
| * | added prefix to FDirection constants, fixing windows build | Miodrag Milanovic | 2018-10-08 | 1 | -11/+11 |
| * | Update CHANGLELOG | Clifford Wolf | 2018-10-08 | 1 | -5/+27 |
| * | Update Changelog | Clifford Wolf | 2018-10-08 | 1 | -1/+54 |
| * | Fix Cygwin build and document needed packages | Miodrag Milanovic | 2018-10-08 | 3 | -1/+14 |
| * | Fixed typo in "verilog_write" help message | acw1251 | 2018-10-08 | 2 | -5/+5 |
| * | Merge remote-tracking branch 'upstream/master' | Jim Lawson | 2018-09-17 | 11 | -14/+78 |
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| | * | Merge pull request #625 from aman-goel/master | Clifford Wolf | 2018-09-14 | 1 | -1/+7 |
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| | | * | Minor revision to -expose in setundef pass | Aman Goel | 2018-09-10 | 1 | -1/+7 |
| | * | | Merge pull request #627 from acw1251/master | Clifford Wolf | 2018-09-14 | 1 | -1/+1 |
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| | | * | | Fixed minor typo in "sim" help message | acw1251 | 2018-09-12 | 1 | -1/+1 |
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| | * | | Add iCE40 SB_SPRAM256KA simulation model | Clifford Wolf | 2018-09-10 | 1 | -9/+30 |
| | * | | Add $lut support to Verilog back-end | Clifford Wolf | 2018-09-06 | 1 | -0/+13 |
| | * | | Add "verific -L <int>" option | Clifford Wolf | 2018-09-04 | 3 | -2/+16 |
| | * | | Add "make ystests" | Clifford Wolf | 2018-08-30 | 3 | -0/+10 |
| | * | | Add GCC to osx deps (#620) | Miodrag Milanović | 2018-08-28 | 1 | -1/+1 |
| * | | | Merge pull request #4 from YosysHQ/master | Jim Lawson | 2018-08-28 | 3 | -23/+112 |
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| | * | | Merge pull request #619 from mmicko/master | Clifford Wolf | 2018-08-28 | 2 | -6/+0 |
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| | | * | | Remove mercurial, since it is not needed anymore | Miodrag Milanovic | 2018-08-28 | 2 | -6/+0 |
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| | * | | Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixes | Clifford Wolf | 2018-08-28 | 1 | -17/+112 |
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| | | * \ | Merge branch 'master' into firrtl+modules+shiftfixes | Jim Lawson | 2018-08-27 | 12 | -39/+92 |
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| * | | | | Merge pull request #3 from YosysHQ/master | Jim Lawson | 2018-08-27 | 12 | -39/+92 |
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| | * | | | Add "make coverage" | Clifford Wolf | 2018-08-27 | 8 | -13/+21 |
| | * | | | Add ENABLE_GCOV build option | Clifford Wolf | 2018-08-27 | 1 | -0/+11 |
| | * | | | Merge pull request #617 from mmicko/master | Clifford Wolf | 2018-08-25 | 1 | -1/+1 |
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| | | * | | | static link flag on main executable | Miodrag Milanovic | 2018-08-25 | 1 | -1/+1 |
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| | * | | | Merge pull request #610 from udif/udif_specify_round2 | Clifford Wolf | 2018-08-23 | 1 | -16/+39 |
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| | | * | | | Fixed all known specify/endspecify issues, without breaking 'make test'. | Udi Finkelstein | 2018-08-20 | 1 | -12/+12 |
| | | * | | | Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout... | Udi Finkelstein | 2018-08-20 | 1 | -10/+22 |
| | | * | | | A few minor enhancements to specify block parsing. | Udi Finkelstein | 2018-08-15 | 1 | -2/+13 |
| | * | | | | Merge pull request #614 from udif/pr_disable_dump_ptr | Clifford Wolf | 2018-08-23 | 3 | -9/+20 |
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| | | * | | | | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 3 | -9/+20 |
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| | | | * | | Remove unused functions. | Jim Lawson | 2018-08-27 | 1 | -10/+0 |
| | | | * | | Add support for module instances. | Jim Lawson | 2018-08-23 | 1 | -17/+122 |
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| * | | | | Merge pull request #1 from YosysHQ/master | Jim Lawson | 2018-08-22 | 196 | -770/+2533 |
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| | * | | | Add "verific -work" help message | Clifford Wolf | 2018-08-22 | 1 | -0/+7 |
| | * | | | Add Verific -work parameter | Clifford Wolf | 2018-08-22 | 1 | -8/+18 |
| | * | | | Merge pull request #606 from cr1901/show-win | Clifford Wolf | 2018-08-19 | 1 | -3/+20 |
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index : iCE40/yosys | |
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