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Age
Files
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Add write address to abc_scc_break of ECP5 dist RAM
Eddie Hung
2019-06-28
1
-1
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+1
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Fix DO4 typo
Eddie Hung
2019-06-28
1
-1
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+1
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Reduce diff with upstream
Eddie Hung
2019-06-27
1
-4
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+2
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Extraneous newline
Eddie Hung
2019-06-27
1
-1
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+0
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Remove noise from ice40/cells_sim.v
Eddie Hung
2019-06-27
1
-5
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+0
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Refactor for one "abc_carry" attribute on module
Eddie Hung
2019-06-27
5
-82
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+84
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung
2019-06-27
2
-0
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+19
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-27
2
-0
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+19
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Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog
Eddie Hung
2019-06-27
2
-0
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+19
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Add simcells.v, simlib.v, and some output
Eddie Hung
2019-06-27
1
-1
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+11
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tests: Check that Icarus can parse arch sim models
David Shah
2019-06-26
2
-0
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+9
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Do not use Module::remove() iterator version
Eddie Hung
2019-06-27
1
-5
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+6
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Remove redundant doc
Eddie Hung
2019-06-27
1
-3
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+0
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Remove &retime when abc9 -fast
Eddie Hung
2019-06-27
1
-1
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+1
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Cleanup abc9.cc
Eddie Hung
2019-06-27
1
-15
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+17
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Undo iterator based Module::remove() for cells, as containers will not
Eddie Hung
2019-06-27
2
-11
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+2
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-27
4
-9
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+39
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Grr
Eddie Hung
2019-06-27
1
-1
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+1
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Capitalisation
Eddie Hung
2019-06-27
1
-1
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+1
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Make CHANGELOG clearer
Eddie Hung
2019-06-27
1
-0
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+1
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Merge pull request #1143 from YosysHQ/clifford/fix1135
Eddie Hung
2019-06-27
4
-8
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+38
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Add #1135 testcase
Eddie Hung
2019-06-27
2
-5
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+26
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Add "pmux2shiftx -norange", fixes #1135
Clifford Wolf
2019-06-27
2
-3
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+12
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-27
0
-0
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+0
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synth_xilinx -arch -> -family, consistent with older synth_intel
Eddie Hung
2019-06-27
1
-7
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+8
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Merge pull request #1142 from YosysHQ/clifford/fix1132
Eddie Hung
2019-06-27
2
-6
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+345
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Copy tests from eddie/fix1132
Eddie Hung
2019-06-27
1
-0
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+320
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Fix handling of partial covers in muxcover, fixes #1132
Clifford Wolf
2019-06-27
1
-6
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+25
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Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux
Eddie Hung
2019-06-27
2
-12
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+34
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Merge pull request #1137 from mmicko/cell_sim_fix
Clifford Wolf
2019-06-26
2
-14
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+1
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Simulation model verilog fix
Miodrag Milanovic
2019-06-26
2
-14
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+1
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Improve opt_clean handling of unused public wires
Clifford Wolf
2019-06-26
1
-2
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+2
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Improve BTOR2 handling of undriven wires
Clifford Wolf
2019-06-26
1
-3
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+27
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Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131
Clifford Wolf
2019-06-26
1
-1
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+1
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Do not clean up buffer cells with "keep" attribute, closes #1128
Clifford Wolf
2019-06-26
1
-1
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+1
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Escape scope names starting with dollar sign in smtio.py
Clifford Wolf
2019-06-26
1
-1
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+4
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Add more ECP5 Diamond flip-flops.
whitequark
2019-06-26
2
-30
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+91
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Add warning if synth_xilinx -abc9 with family != xc7
Eddie Hung
2019-06-27
1
-0
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+2
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Remove unneeded include
Eddie Hung
2019-06-27
1
-3
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+0
*
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Merge origin/master
Eddie Hung
2019-06-27
10
-65
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+480
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Fix spacing
Eddie Hung
2019-06-26
1
-38
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+38
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Improve debugging message for comb loops
Eddie Hung
2019-06-26
1
-4
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+6
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Add WE to ECP5 dist RAM's abc_scc_break too
Eddie Hung
2019-06-26
1
-1
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+1
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Update comment on boxes
Eddie Hung
2019-06-26
2
-4
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+6
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Add "WE" to dist RAM's abc_scc_break
Eddie Hung
2019-06-26
1
-3
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+3
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Support more than one port in the abc_scc_break attr
Eddie Hung
2019-06-26
1
-38
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+42
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Add write_xaiger into CHANGELOG
Eddie Hung
2019-06-26
1
-0
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+1
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Merge branch 'koriakin/xc7nocarrymux' into xaig
Eddie Hung
2019-06-26
0
-0
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+0
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Grrr
Eddie Hung
2019-06-26
1
-2
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+2
*
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Remove unused var
Eddie Hung
2019-06-26
1
-1
/
+1
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