From 2e51dc1856aae456e15cafd484997bfbd102175e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Feb 2020 13:06:13 -0800 Subject: verilog: ignore '&&&' when not in -specify mode --- tests/various/specify.v | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index 5006e4c38..aa8aca4bc 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -51,3 +51,9 @@ specify $setuphold(d, posedge clk, 1:2:3, 4:5:6); endspecify endmodule + +module test5(input clk, d, e, output q); +specify + $setup(d, posedge clk &&& e, 1:2:3); +endspecify +endmodule -- cgit v1.2.3