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-rw-r--r--tests/sva/sva_throughout.sv (renamed from tests/sva/sva_until.sv)2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/sva/sva_until.sv b/tests/sva/sva_throughout.sv
index a721e44b5..7e036a066 100644
--- a/tests/sva/sva_until.sv
+++ b/tests/sva/sva_throughout.sv
@@ -5,7 +5,7 @@ module top (
default clocking @(posedge clk); endclocking
assert property (
- a |=> b until_with (c ##1 d)
+ a |=> b throughout (c ##1 d)
);
`ifndef FAIL