From 6d12c83d362c709f72e64eea2121b2cffc12ee8d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 21 Feb 2018 13:09:47 +0100 Subject: Add support for SVA throughout via Verific --- tests/sva/sva_throughout.sv | 19 +++++++++++++++++++ tests/sva/sva_until.sv | 19 ------------------- 2 files changed, 19 insertions(+), 19 deletions(-) create mode 100644 tests/sva/sva_throughout.sv delete mode 100644 tests/sva/sva_until.sv (limited to 'tests/sva') diff --git a/tests/sva/sva_throughout.sv b/tests/sva/sva_throughout.sv new file mode 100644 index 000000000..7e036a066 --- /dev/null +++ b/tests/sva/sva_throughout.sv @@ -0,0 +1,19 @@ +module top ( + input clk, + input a, b, c, d +); + default clocking @(posedge clk); endclocking + + assert property ( + a |=> b throughout (c ##1 d) + ); + +`ifndef FAIL + assume property ( + a |=> b && c + ); + assume property ( + b && c |=> b && d + ); +`endif +endmodule diff --git a/tests/sva/sva_until.sv b/tests/sva/sva_until.sv deleted file mode 100644 index a721e44b5..000000000 --- a/tests/sva/sva_until.sv +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clk, - input a, b, c, d -); - default clocking @(posedge clk); endclocking - - assert property ( - a |=> b until_with (c ##1 d) - ); - -`ifndef FAIL - assume property ( - a |=> b && c - ); - assume property ( - b && c |=> b && d - ); -`endif -endmodule -- cgit v1.2.3