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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-05-06 16:30:56 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
commit | 982a11c709b4b363f85ae52a127f8a98bda30a3f (patch) | |
tree | de2dd78747314064b3a7731fc4791b0ec7bfb77d /tests/memlib/memlib_wide_sp.txt | |
parent | 2a2dc12eb69f2e904609e5b8275ec885e21ecd26 (diff) | |
download | yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.tar.gz yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.tar.bz2 yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.zip |
Add memory_libmap tests.
Diffstat (limited to 'tests/memlib/memlib_wide_sp.txt')
-rw-r--r-- | tests/memlib/memlib_wide_sp.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/memlib/memlib_wide_sp.txt b/tests/memlib/memlib_wide_sp.txt new file mode 100644 index 000000000..7780e4f9d --- /dev/null +++ b/tests/memlib/memlib_wide_sp.txt @@ -0,0 +1,22 @@ +ram block \RAM_WIDE_SP { + cost 2; + abits 6; + widths 1 2 5 10 20 per_port; + byte 5; + init any; + port srsw "A" { + ifdef WIDTH_MIX { + option "WIDTH_MIX" 1 { + width mix; + } + } else { + option "WIDTH_MIX" 0 { + width tied; + } + } + clock posedge; + rden; + rdwr old; + rdsrst any ungated; + } +} |