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-rw-r--r--techlibs/xilinx/abc_map.v26
-rw-r--r--techlibs/xilinx/abc_model.v60
-rw-r--r--techlibs/xilinx/abc_unmap.v96
-rw-r--r--techlibs/xilinx/abc_xc7.box4
-rw-r--r--techlibs/xilinx/cells_sim.v9
-rw-r--r--techlibs/xilinx/synth_xilinx.cc2
6 files changed, 26 insertions, 171 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 121862692..c3701b1a8 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -31,7 +31,7 @@ module RAM32X1D (
parameter INIT = 32'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire \$DPO , \$SPO ;
- \$__ABC_RAM32X1D #(
+ RAM32X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO(\$DPO ), .SPO(\$SPO ),
@@ -39,8 +39,8 @@ module RAM32X1D (
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
);
- \$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
- \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
+ \$__ABC_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
+ \$__ABC_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
endmodule
module RAM64X1D (
@@ -54,7 +54,7 @@ module RAM64X1D (
parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire \$DPO , \$SPO ;
- \$__ABC_RAM64X1D #(
+ RAM64X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO(\$DPO ), .SPO(\$SPO ),
@@ -62,8 +62,8 @@ module RAM64X1D (
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
);
- \$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
- \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
+ \$__ABC_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
+ \$__ABC_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
endmodule
module RAM128X1D (
@@ -76,7 +76,7 @@ module RAM128X1D (
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire \$DPO , \$SPO ;
- \$__ABC_RAM128X1D #(
+ RAM128X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO(\$DPO ), .SPO(\$SPO ),
@@ -84,8 +84,8 @@ module RAM128X1D (
.A(A),
.DPRA(DPRA)
);
- \$__ABC_LUTMUX7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
- \$__ABC_LUTMUX7 spo (.A(\$SPO ), .S(A), .Y(SPO));
+ \$__ABC_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
+ \$__ABC_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
endmodule
module SRL16E (
@@ -95,14 +95,14 @@ module SRL16E (
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
wire \$Q ;
- \$__ABC_SRL16E #(
+ SRL16E #(
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.Q(\$Q ),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
);
// TODO: Check if SRL uses fast inputs or slow inputs
- \$__ABC_LUTMUX6 q (.A(\$Q ), .S({A0, A1, A2, A3, 1'b0, 1'b0}), .Y(Q));
+ \$__ABC_LUT6 q (.A(\$Q ), .S({A0, A1, A2, A3, 1'b0, 1'b0}), .Y(Q));
endmodule
module SRLC32E (
@@ -114,12 +114,12 @@ module SRLC32E (
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
wire \$Q ;
- \$__ABC_SRLC32E #(
+ SRLC32E #(
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.Q(\$Q ), .Q31(Q31),
.A(A), .CE(CE), .CLK(CLK), .D(D)
);
// TODO: Check if SRL uses fast inputs or slow inputs
- \$__ABC_LUTMUX6 q (.A(\$Q ), .S({A, 1'b0}), .Y(Q));
+ \$__ABC_LUT6 q (.A(\$Q ), .S({A, 1'b0}), .Y(Q));
endmodule
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index e3e9686b5..655b993f6 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -27,64 +27,8 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
endmodule
(* abc_box_id=2000 *)
-module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
+module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
endmodule
(* abc_box_id=2001 *)
-module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
-endmodule
-
-module \$__ABC_RAM32X1D (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
- (* abc_arrival=1153 *) output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A0, A1, A2, A3, A4,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
-);
-endmodule
-
-module \$__ABC_RAM64X1D (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
- (* abc_arrival=1153 *) output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A0, A1, A2, A3, A4, A5,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
-);
- parameter INIT = 64'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
-endmodule
-
-module \$__ABC_RAM128X1D (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
- (* abc_arrival=1153 *) output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input [6:0] A, DPRA
-);
- parameter INIT = 128'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
-endmodule
-
-module SRL16E (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
- (* abc_arrival=1472 *) output Q,
- input A0, A1, A2, A3, CE, CLK, D
-);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
-endmodule
-
-module SRLC32E (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
- (* abc_arrival=1472 *) output Q,
- (* abc_arrival=1114 *) output Q31,
- input [4:0] A,
- input CE, CLK, D
-);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
+module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
endmodule
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
index 779fc5aac..f101a22d0 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@ -20,101 +20,9 @@
// ============================================================================
-module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
+module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
assign Y = A;
endmodule
-module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
+module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
assign Y = A;
endmodule
-
-module \$__ABC_RAM32X1D (
- output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A0, A1, A2, A3, A4,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
-);
- parameter INIT = 32'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
- RAM32X1D #(
- .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .DPO(DPO), .SPO(SPO),
- .D(D), .WCLK(WCLK), .WE(WE),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
- .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
- );
-endmodule
-
-module \$__ABC_RAM64X1D (
- output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A0, A1, A2, A3, A4, A5,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
-);
- parameter INIT = 64'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
- RAM64X1D #(
- .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .DPO(DPO), .SPO(SPO),
- .D(D), .WCLK(WCLK), .WE(WE),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
- .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
- );
-endmodule
-
-module \$__ABC_RAM128X1D (
- output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A,
- input DPRA,
-);
- parameter INIT = 128'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
- RAM128X1D #(
- .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .DPO(DPO), .SPO(SPO),
- .D(D), .WCLK(WCLK), .WE(WE),
- .A(A),
- .DPRA(DPRA)
- );
-endmodule
-
-module \$__ABC_SRL16E (
- output Q,
- input A0, A1, A2, A3, CE, CLK, D
-);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
-
- SRL16E #(
- .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .Q(Q),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
- );
-endmodule
-
-module \$__ABC_SRLC32E (
- output Q,
- output Q31,
- input [4:0] A,
- input CE, CLK, D
-);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
-
- SRLC32E #(
- .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .Q(Q), .Q31(Q31),
- .A(A), .CE(CE), .CLK(CLK), .D(D)
- );
-endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 61b89b8af..554cc0cf0 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -42,12 +42,12 @@ CARRY4 4 1 10 8
# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
# Inputs: A S0 S1 S2 S3 S4 S5
# Outputs: Y
-$__ABC_LUTRAM6 2000 0 7 1
+$__ABC_LUT6 2000 0 7 1
0 642 631 472 407 238 127
# SLICEM/A6LUT + F7BMUX
# Box to emulate comb/seq behaviour of RAMD128
# Inputs: A S0 S1 S2 S3 S4 S5 S6
# Outputs: DPO SPO
-$__ABC_LUTRAM7 2001 0 8 1
+$__ABC_LUT7 2001 0 8 1
0 1047 1036 877 812 643 532 478
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 6aba5a4b2..3a58f32fa 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -298,7 +298,8 @@ module FDPE_1 ((* abc_arrival=303 *) output reg Q,
endmodule
module RAM32X1D (
- output DPO, SPO,
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=11530 *) output DPO, SPO,
input D,
input WCLK,
input WE,
@@ -317,7 +318,8 @@ module RAM32X1D (
endmodule
module RAM64X1D (
- output DPO, SPO,
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=1153 *) output DPO, SPO,
input D,
input WCLK,
input WE,
@@ -336,7 +338,8 @@ module RAM64X1D (
endmodule
module RAM128X1D (
- output DPO, SPO,
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=1153 *) output DPO, SPO,
input D,
input WCLK,
input WE,
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b9c4df82f..263788fec 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -391,7 +391,7 @@ struct SynthXilinxPass : public ScriptPass
if (family != "xc7")
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
run("read_verilog -icells -lib +/xilinx/abc_model.v");
- run("techmap -map +/xilinx/abc_map.v");
+ run("techmap -map +/xilinx/abc_map.v -max_iter 1");
if (nowidelut)
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
else
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-03 20:03:37 +0000