From c26c5563845d81048dea35c4aef5f4678e177b23 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 19:47:11 -0700 Subject: xilinx to use abc_map.v with -max_iter 1 --- techlibs/xilinx/cells_sim.v | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'techlibs/xilinx/cells_sim.v') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 6aba5a4b2..3a58f32fa 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -298,7 +298,8 @@ module FDPE_1 ((* abc_arrival=303 *) output reg Q, endmodule module RAM32X1D ( - output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc_arrival=11530 *) output DPO, SPO, input D, input WCLK, input WE, @@ -317,7 +318,8 @@ module RAM32X1D ( endmodule module RAM64X1D ( - output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc_arrival=1153 *) output DPO, SPO, input D, input WCLK, input WE, @@ -336,7 +338,8 @@ module RAM64X1D ( endmodule module RAM128X1D ( - output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc_arrival=1153 *) output DPO, SPO, input D, input WCLK, input WE, -- cgit v1.2.3