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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-19 09:51:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-19 09:51:11 -0700 |
| commit | 96ade549932ca48d0e1d3b99389129cdc37524a0 (patch) | |
| tree | df554391c3f2c867339fcdaa07e39bdba8c97cec /CHANGELOG | |
| parent | 8395f837c33a1f08ed67995ef8274219b0af27c8 (diff) | |
| download | yosys-96ade549932ca48d0e1d3b99389129cdc37524a0.tar.gz yosys-96ade549932ca48d0e1d3b99389129cdc37524a0.tar.bz2 yosys-96ade549932ca48d0e1d3b99389129cdc37524a0.zip | |
Fix bug in #1078, add entry to CHANGELOG
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -17,6 +17,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "rename -src" - Added "equiv_opt" pass - Added "read_aiger" frontend + - Extended "muxcover -mux{4,8,16}=<cost>" - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" |