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authorClifford Wolf <clifford@clifford.at>2019-06-19 17:25:39 +0200
committerGitHub <noreply@github.com>2019-06-19 17:25:39 +0200
commit8395f837c33a1f08ed67995ef8274219b0af27c8 (patch)
treee4fa22a4a4598e86f0fa324741fb6062dca851e8 /CHANGELOG
parent5a1f1caa44fb3f4427813acab61aaecc06bae7ba (diff)
parentec4565009ae69409eb01f1b595f5f59fcc969ce2 (diff)
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Merge pull request #1109 from YosysHQ/clifford/fix1106
Add "read_verilog -pwires" feature
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