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Diffstat (limited to 'tests/arch/ice40/alu.ys')
| -rw-r--r-- | tests/arch/ice40/alu.ys | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/tests/arch/ice40/alu.ys b/tests/arch/ice40/alu.ys deleted file mode 100644 index bd859efc4..000000000 --- a/tests/arch/ice40/alu.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_CARRY -select -assert-count 32 t:SB_DFF -select -assert-count 655 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D |