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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-04-04 11:18:24 +0200 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-04-06 09:10:14 +0200 |
| commit | 0f5e7c244df1bb0d4b41bd54d4d5791e653ed448 (patch) | |
| tree | 9632456841d6b5e69740c1ec565457dcb0af1518 | |
| parent | 54d313efc3bc6745bea6752830de65107d1d8f2a (diff) | |
| download | yosys-0f5e7c244df1bb0d4b41bd54d4d5791e653ed448.tar.gz yosys-0f5e7c244df1bb0d4b41bd54d4d5791e653ed448.tar.bz2 yosys-0f5e7c244df1bb0d4b41bd54d4d5791e653ed448.zip | |
add additional dff and lutram tests
| -rw-r--r-- | tests/arch/machxo2/adffs.ys | 40 | ||||
| -rw-r--r-- | tests/arch/machxo2/lutram.ys | 17 |
2 files changed, 57 insertions, 0 deletions
diff --git a/tests/arch/machxo2/adffs.ys b/tests/arch/machxo2/adffs.ys new file mode 100644 index 000000000..a9f8980c6 --- /dev/null +++ b/tests/arch/machxo2/adffs.ys @@ -0,0 +1,40 @@ +read_verilog ../common/adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/arch/machxo2/lutram.ys b/tests/arch/machxo2/lutram.ys new file mode 100644 index 000000000..dc6b86fd3 --- /dev/null +++ b/tests/arch/machxo2/lutram.ys @@ -0,0 +1,17 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 -noiopad +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 20 t:LUT4 +select -assert-count 8 t:TRELLIS_DPR16X4 +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D |