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-rw-r--r--tests/arch/machxo2/lutram.ys17
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/arch/machxo2/lutram.ys b/tests/arch/machxo2/lutram.ys
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index 000000000..dc6b86fd3
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+++ b/tests/arch/machxo2/lutram.ys
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+read_verilog ../common/lutram.v
+hierarchy -top lutram_1w1r
+proc
+memory -nomap
+equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 -noiopad
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd lutram_1w1r
+select -assert-count 20 t:LUT4
+select -assert-count 8 t:TRELLIS_DPR16X4
+select -assert-count 8 t:TRELLIS_FF
+select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D