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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-04-04 10:56:28 +0200 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-04-06 09:10:14 +0200 |
| commit | 54d313efc3bc6745bea6752830de65107d1d8f2a (patch) | |
| tree | f9d9a2f2d77db81e617bd25ddde7ccc078f8e5cc | |
| parent | 9e9fae19662b87c773f435849ea6f2591e9e8900 (diff) | |
| download | yosys-54d313efc3bc6745bea6752830de65107d1d8f2a.tar.gz yosys-54d313efc3bc6745bea6752830de65107d1d8f2a.tar.bz2 yosys-54d313efc3bc6745bea6752830de65107d1d8f2a.zip | |
add test for CCU2D
| -rw-r--r-- | tests/arch/machxo2/counter.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/arch/machxo2/counter.ys b/tests/arch/machxo2/counter.ys new file mode 100644 index 000000000..54ee80066 --- /dev/null +++ b/tests/arch/machxo2/counter.ys @@ -0,0 +1,10 @@ +read_verilog ../common/counter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -multiclock -map +/machxo2/cells_sim.v synth_machxo2 -ccu2 -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:CCU2D +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:CCU2D t:TRELLIS_FF %% t:* %D |