aboutsummaryrefslogtreecommitdiffstats
path: root/ice40
Commit message (Collapse)AuthorAgeFilesLines
* ice40: Fix carry packer bugDavid Shah2018-09-251-2/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge pull request #56 from YosysHQ/q3k/issue-55Serge Bazanski2018-08-192-12/+28
|\ | | | | ice40: make PLL packing more robust
| * ice40: make PLL packing more robustSergiusz Bazanski2018-08-192-12/+28
| |
* | Add more missing iCE40 gfx (LP/HX is complete now)Clifford Wolf2018-08-193-4/+47
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add iCE40 gfx for carry chain pips and LUT cascade pipsClifford Wolf2018-08-191-5/+43
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix iCE40 pip gfx for pips on the top edge of a switchboxClifford Wolf2018-08-191-5/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add iCE40 gfx for IO span-4 cornersClifford Wolf2018-08-193-3/+36
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add iCE40 gfx for span-4 wires between IO tilesClifford Wolf2018-08-195-7/+126
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-184-16/+5
|\ | | | | Use settings for placer1 and router1
| * Save settings and give nicer names to someMiodrag Milanovic2018-08-102-3/+3
| |
| * Use settings for placer1 and router1Miodrag Milanovic2018-08-092-13/+2
| |
* | Add iCE40 gfx for wires connecting fabric tiles and IO tilesClifford Wolf2018-08-184-2/+261
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve iCE40 gfx for IO tiles and RAM tilesClifford Wolf2018-08-185-23/+243
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add ice40 wire attributes (grid position, segment list)Clifford Wolf2018-08-183-18/+45
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge branch 'master' of github.com:YosysHQ/nextpnr into archattrClifford Wolf2018-08-181-4/+6
|\ \
| * | do not break if there are no nets loaded from sym sectionMiodrag Milanovic2018-08-181-4/+6
| | |
* | | Add Arch attrs APIClifford Wolf2018-08-141-0/+18
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into placer_speedupEddie Hung2018-08-101-1/+11
|\|
| * Merge pull request #42 from YosysHQ/floorplanDavid Shah2018-08-091-1/+11
| |\ | | | | | | Add basic data structures for floorplanning
| | * Add pip locationsClifford Wolf2018-08-091-1/+11
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of ↵Eddie Hung2018-08-103-17/+18
| | | | | | | | | | | | std::array
* | | Make containers staticEddie Hung2018-08-091-5/+7
|/ /
* | ice40: Speedup Arch::predictDelay() with pass-by-refEddie Hung2018-08-081-1/+1
| |
* | Use settings for json and pcfMiodrag Milanovic2018-08-084-8/+12
|/
* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-085-389/+270
|\
| * Merge pull request #44 from YosysHQ/improve_timing_specDavid Shah2018-08-082-32/+89
| |\ | | | | | | Speed up budget allocator using topographical ordering and update cell timing API
| | * ice40: Add error for unknown cell type when getting timing infoDavid Shah2018-08-081-1/+3
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * Arch API: Removing Arch::isIOCellDavid Shah2018-08-082-4/+0
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * ice40: Add timing arcs through global buffersDavid Shah2018-08-081-0/+4
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * timing: Debugging implementation of new timing APIDavid Shah2018-08-081-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * ice40: Timing arch fixDavid Shah2018-08-081-3/+17
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * timing: Update to new use API (currently broken)David Shah2018-08-081-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * Arch API: New specification for timing port classesDavid Shah2018-08-082-22/+52
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * clangformatEddie Hung2018-08-062-16/+20
| | |
| | * Merge branch 'master' into assign_budget_speedupEddie Hung2018-08-061-2/+17
| | |\
| | * | Add new Arch::isIOCell() API functionEddie Hung2018-08-062-0/+7
| | | |
| * | | Moved option to commonMiodrag Milanovic2018-08-081-1/+0
| | | |
| * | | clangformatMiodrag Milanovic2018-08-081-4/+4
| | | |
| * | | Merge remote-tracking branch 'origin/master' into common_mainMiodrag Milanovic2018-08-085-100/+114
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | # Conflicts: # ecp5/main.cc # ice40/main.cc
| * | | Added project loaderMiodrag Milanovic2018-08-062-0/+72
| | | |
| * | | Fix message for pcf loadingMiodrag Milanovic2018-08-051-1/+1
| | | |
| * | | Added command parser and common implementationMiodrag Milanovic2018-08-051-355/+111
| | | |
* | | | Get rid of old iCE40 id_ Arch membersClifford Wolf2018-08-086-59/+36
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-0811-257/+125
| |/ / |/| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | ice40's getBudgetOverride() to return correct delay for different devicesEddie Hung2018-08-061-2/+17
| |/ |/|
* | Fix ice40's getBudgetOverride() to override only for COUT -> CINEddie Hung2018-08-061-1/+1
| |
* | Change getBudgetOverride() signature to return bool and modify budget in placeEddie Hung2018-08-062-5/+7
| |
* | Restore initial assign_budget() call after pack(), restrict call after ↵Eddie Hung2018-08-051-0/+1
| | | | | | | | initial_placement to slack_redist
* | API change: Use CellInfo* and NetInfo* as cell/net handles (Python bindings)David Shah2018-08-051-9/+9
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-054-85/+82
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 12:50:29 +0000