Merge remote-tracking branch 'origin/master' into common_main

# Conflicts:
#	ecp5/main.cc
#	ice40/main.cc

5 files changed, 114 insertions, 100 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index 5d79a487..fcc9d798 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -637,17 +637,34 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
 
 // -----------------------------------------------------------------------
 
-delay_t Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const
+bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
 {
     const auto &driver = net_info->driver;
-    if (driver.port == id_cout) {
+    if (driver.port == id_cout && sink.port == id_cin) {
         auto driver_loc = getBelLocation(driver.cell->bel);
         auto sink_loc = getBelLocation(sink.cell->bel);
         if (driver_loc.y == sink_loc.y)
-            return 0;
-        return 250;
+            budget = 0;
+        else switch (args.type) {
+#ifndef ICE40_HX1K_ONLY
+            case ArchArgs::HX8K:
+#endif
+            case ArchArgs::HX1K:
+                budget = 190; break;
+#ifndef ICE40_HX1K_ONLY
+            case ArchArgs::LP384:
+            case ArchArgs::LP1K:
+            case ArchArgs::LP8K:
+                budget = 290; break;
+            case ArchArgs::UP5K:
+                budget = 560; break;
+#endif
+            default:
+                log_error("Unsupported iCE40 chip type.\n");
+        }
+        return true;
     }
-    return budget;
+    return false;
 }
 
 // -----------------------------------------------------------------------
@@ -672,7 +689,7 @@ DecalXY Arch::getBelDecal(BelId bel) const
     DecalXY decalxy;
     decalxy.decal.type = DecalId::TYPE_BEL;
     decalxy.decal.index = bel.index;
-    decalxy.decal.active = bel_to_cell.at(bel.index) != IdString();
+    decalxy.decal.active = bel_to_cell.at(bel.index) != nullptr;
     return decalxy;
 }
 
@@ -681,7 +698,7 @@ DecalXY Arch::getWireDecal(WireId wire) const
     DecalXY decalxy;
     decalxy.decal.type = DecalId::TYPE_WIRE;
     decalxy.decal.index = wire.index;
-    decalxy.decal.active = wire_to_net.at(wire.index) != IdString();
+    decalxy.decal.active = wire_to_net.at(wire.index) != nullptr;
     return decalxy;
 }
 
@@ -690,7 +707,7 @@ DecalXY Arch::getPipDecal(PipId pip) const
     DecalXY decalxy;
     decalxy.decal.type = DecalId::TYPE_PIP;
     decalxy.decal.index = pip.index;
-    decalxy.decal.active = pip_to_net.at(pip.index) != IdString();
+    decalxy.decal.active = pip_to_net.at(pip.index) != nullptr;
     return decalxy;
 };
 
diff --git a/ice40/arch.h b/ice40/arch.h
index bc968b74..73f1ea0e 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -400,10 +400,10 @@ struct Arch : BaseCtx
     mutable std::unordered_map<Loc, int> bel_by_loc;
 
     std::vector<bool> bel_carry;
-    std::vector<IdString> bel_to_cell;
-    std::vector<IdString> wire_to_net;
-    std::vector<IdString> pip_to_net;
-    std::vector<IdString> switches_locked;
+    std::vector<CellInfo*> bel_to_cell;
+    std::vector<NetInfo*> wire_to_net;
+    std::vector<NetInfo*> pip_to_net;
+    std::vector<NetInfo*> switches_locked;
 
     ArchArgs args;
     Arch(ArchArgs args);
@@ -438,26 +438,25 @@ struct Arch : BaseCtx
 
     uint32_t getBelChecksum(BelId bel) const { return bel.index; }
 
-    void bindBel(BelId bel, IdString cell, PlaceStrength strength)
+    void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
     {
         NPNR_ASSERT(bel != BelId());
-        NPNR_ASSERT(bel_to_cell[bel.index] == IdString());
-        auto &c = cells[cell];
+        NPNR_ASSERT(bel_to_cell[bel.index] == nullptr);
 
         bel_to_cell[bel.index] = cell;
-        bel_carry[bel.index] = (c->type == id_icestorm_lc && c->lcInfo.carryEnable);
-        c->bel = bel;
-        c->belStrength = strength;
+        bel_carry[bel.index] = (cell->type == id_icestorm_lc && cell->lcInfo.carryEnable);
+        cell->bel = bel;
+        cell->belStrength = strength;
         refreshUiBel(bel);
     }
 
     void unbindBel(BelId bel)
     {
         NPNR_ASSERT(bel != BelId());
-        NPNR_ASSERT(bel_to_cell[bel.index] != IdString());
-        cells[bel_to_cell[bel.index]]->bel = BelId();
-        cells[bel_to_cell[bel.index]]->belStrength = STRENGTH_NONE;
-        bel_to_cell[bel.index] = IdString();
+        NPNR_ASSERT(bel_to_cell[bel.index] != nullptr);
+        bel_to_cell[bel.index]->bel = BelId();
+        bel_to_cell[bel.index]->belStrength = STRENGTH_NONE;
+        bel_to_cell[bel.index] = nullptr;
         bel_carry[bel.index] = false;
         refreshUiBel(bel);
     }
@@ -465,16 +464,16 @@ struct Arch : BaseCtx
     bool checkBelAvail(BelId bel) const
     {
         NPNR_ASSERT(bel != BelId());
-        return bel_to_cell[bel.index] == IdString();
+        return bel_to_cell[bel.index] == nullptr;
     }
 
-    IdString getBoundBelCell(BelId bel) const
+    CellInfo *getBoundBelCell(BelId bel) const
     {
         NPNR_ASSERT(bel != BelId());
         return bel_to_cell[bel.index];
     }
 
-    IdString getConflictingBelCell(BelId bel) const
+    CellInfo *getConflictingBelCell(BelId bel) const
     {
         NPNR_ASSERT(bel != BelId());
         return bel_to_cell[bel.index];
@@ -526,49 +525,49 @@ struct Arch : BaseCtx
 
     uint32_t getWireChecksum(WireId wire) const { return wire.index; }
 
-    void bindWire(WireId wire, IdString net, PlaceStrength strength)
+    void bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
     {
         NPNR_ASSERT(wire != WireId());
-        NPNR_ASSERT(wire_to_net[wire.index] == IdString());
+        NPNR_ASSERT(wire_to_net[wire.index] == nullptr);
         wire_to_net[wire.index] = net;
-        nets[net]->wires[wire].pip = PipId();
-        nets[net]->wires[wire].strength = strength;
+        net->wires[wire].pip = PipId();
+        net->wires[wire].strength = strength;
         refreshUiWire(wire);
     }
 
     void unbindWire(WireId wire)
     {
         NPNR_ASSERT(wire != WireId());
-        NPNR_ASSERT(wire_to_net[wire.index] != IdString());
+        NPNR_ASSERT(wire_to_net[wire.index] != nullptr);
 
-        auto &net_wires = nets[wire_to_net[wire.index]]->wires;
+        auto &net_wires = wire_to_net[wire.index]->wires;
         auto it = net_wires.find(wire);
         NPNR_ASSERT(it != net_wires.end());
 
         auto pip = it->second.pip;
         if (pip != PipId()) {
-            pip_to_net[pip.index] = IdString();
-            switches_locked[chip_info->pip_data[pip.index].switch_index] = IdString();
+            pip_to_net[pip.index] = nullptr;
+            switches_locked[chip_info->pip_data[pip.index].switch_index] = nullptr;
         }
 
         net_wires.erase(it);
-        wire_to_net[wire.index] = IdString();
+        wire_to_net[wire.index] = nullptr;
         refreshUiWire(wire);
     }
 
     bool checkWireAvail(WireId wire) const
     {
         NPNR_ASSERT(wire != WireId());
-        return wire_to_net[wire.index] == IdString();
+        return wire_to_net[wire.index] == nullptr;
     }
 
-    IdString getBoundWireNet(WireId wire) const
+    NetInfo *getBoundWireNet(WireId wire) const
     {
         NPNR_ASSERT(wire != WireId());
         return wire_to_net[wire.index];
     }
 
-    IdString getConflictingWireNet(WireId wire) const
+    NetInfo *getConflictingWireNet(WireId wire) const
     {
         NPNR_ASSERT(wire != WireId());
         return wire_to_net[wire.index];
@@ -606,21 +605,21 @@ struct Arch : BaseCtx
 
     PipId getPipByName(IdString name) const;
 
-    void bindPip(PipId pip, IdString net, PlaceStrength strength)
+    void bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
     {
         NPNR_ASSERT(pip != PipId());
-        NPNR_ASSERT(pip_to_net[pip.index] == IdString());
-        NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString());
+        NPNR_ASSERT(pip_to_net[pip.index] == nullptr);
+        NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] == nullptr);
 
         pip_to_net[pip.index] = net;
         switches_locked[chip_info->pip_data[pip.index].switch_index] = net;
 
         WireId dst;
         dst.index = chip_info->pip_data[pip.index].dst;
-        NPNR_ASSERT(wire_to_net[dst.index] == IdString());
+        NPNR_ASSERT(wire_to_net[dst.index] == nullptr);
         wire_to_net[dst.index] = net;
-        nets[net]->wires[dst].pip = pip;
-        nets[net]->wires[dst].strength = strength;
+        net->wires[dst].pip = pip;
+        net->wires[dst].strength = strength;
         refreshUiPip(pip);
         refreshUiWire(dst);
     }
@@ -628,17 +627,17 @@ struct Arch : BaseCtx
     void unbindPip(PipId pip)
     {
         NPNR_ASSERT(pip != PipId());
-        NPNR_ASSERT(pip_to_net[pip.index] != IdString());
-        NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] != IdString());
+        NPNR_ASSERT(pip_to_net[pip.index] != nullptr);
+        NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] != nullptr);
 
         WireId dst;
         dst.index = chip_info->pip_data[pip.index].dst;
-        NPNR_ASSERT(wire_to_net[dst.index] != IdString());
-        wire_to_net[dst.index] = IdString();
-        nets[pip_to_net[pip.index]]->wires.erase(dst);
+        NPNR_ASSERT(wire_to_net[dst.index] != nullptr);
+        wire_to_net[dst.index] = nullptr;
+        pip_to_net[pip.index]->wires.erase(dst);
 
-        pip_to_net[pip.index] = IdString();
-        switches_locked[chip_info->pip_data[pip.index].switch_index] = IdString();
+        pip_to_net[pip.index] = nullptr;
+        switches_locked[chip_info->pip_data[pip.index].switch_index] = nullptr;
         refreshUiPip(pip);
         refreshUiWire(dst);
     }
@@ -649,12 +648,12 @@ struct Arch : BaseCtx
         auto &pi = chip_info->pip_data[pip.index];
         auto &si = chip_info->bits_info->switches[pi.switch_index];
 
-        if (switches_locked[pi.switch_index] != IdString())
+        if (switches_locked[pi.switch_index] != nullptr)
             return false;
 
         if (pi.flags & PipInfoPOD::FLAG_ROUTETHRU) {
             NPNR_ASSERT(si.bel >= 0);
-            if (bel_to_cell[si.bel] != IdString())
+            if (bel_to_cell[si.bel] != nullptr)
                 return false;
         }
 
@@ -667,13 +666,13 @@ struct Arch : BaseCtx
         return true;
     }
 
-    IdString getBoundPipNet(PipId pip) const
+    NetInfo *getBoundPipNet(PipId pip) const
     {
         NPNR_ASSERT(pip != PipId());
         return pip_to_net[pip.index];
     }
 
-    IdString getConflictingPipNet(PipId pip) const
+    NetInfo *getConflictingPipNet(PipId pip) const
     {
         NPNR_ASSERT(pip != PipId());
         return switches_locked[chip_info->pip_data[pip.index].switch_index];
@@ -768,7 +767,7 @@ struct Arch : BaseCtx
     delay_t getRipupDelayPenalty() const { return 200; }
     float getDelayNS(delay_t v) const { return v * 0.001; }
     uint32_t getDelayChecksum(delay_t v) const { return v; }
-    delay_t getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const;
+    bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
 
     // -------------------------------------------------
 
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index b3404d6c..274dc1d3 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -74,19 +74,18 @@ bool Arch::isBelLocationValid(BelId bel) const
         std::vector<const CellInfo *> bel_cells;
         Loc bel_loc = getBelLocation(bel);
         for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
-            IdString cell_other = getBoundBelCell(bel_other);
-            if (cell_other != IdString()) {
-                const CellInfo *ci_other = cells.at(cell_other).get();
+            CellInfo *ci_other = getBoundBelCell(bel_other);
+            if (ci_other != nullptr) {
                 bel_cells.push_back(ci_other);
             }
         }
         return logicCellsCompatible(bel_cells);
     } else {
-        IdString cellId = getBoundBelCell(bel);
-        if (cellId == IdString())
+        CellInfo *ci = getBoundBelCell(bel);
+        if (ci == nullptr)
             return true;
         else
-            return isValidBelForCell(cells.at(cellId).get(), bel);
+            return isValidBelForCell(ci, bel);
     }
 }
 
@@ -98,9 +97,8 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
         std::vector<const CellInfo *> bel_cells;
         Loc bel_loc = getBelLocation(bel);
         for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
-            IdString cell_other = getBoundBelCell(bel_other);
-            if (cell_other != IdString() && bel_other != bel) {
-                const CellInfo *ci_other = cells.at(cell_other).get();
+            CellInfo *ci_other = getBoundBelCell(bel_other);
+            if (ci_other != nullptr && bel_other != bel) {
                 bel_cells.push_back(ci_other);
             }
         }
@@ -126,12 +124,12 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
         if (pll_bel.index != -1) {
             auto pll_cell = getBoundBelCell(pll_bel);
             // Is a PLL placed in this PLL bel?
-            if (pll_cell != IdString()) {
+            if (pll_cell != nullptr) {
                 // Is the shared port driving a net?
-                auto pi = cells.at(pll_cell)->ports[portPinToId(pll_bel_pin)];
+                auto pi = pll_cell->ports[portPinToId(pll_bel_pin)];
                 if (pi.net != nullptr) {
                     // Are we perhaps a PAD INPUT Bel that can be placed here?
-                    if (cells.at(pll_cell)->attrs[id("BEL_PAD_INPUT")] == getBelName(bel).str(this)) {
+                    if (pll_cell->attrs[id("BEL_PAD_INPUT")] == getBelName(bel).str(this)) {
                         return true;
                     }
                     return false;
diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc
index 98164e87..1d16ade0 100644
--- a/ice40/arch_pybindings.cc
+++ b/ice40/arch_pybindings.cc
@@ -70,13 +70,13 @@ void arch_wrap_python()
     fn_wrapper_1a<Context, decltype(&Context::getBelChecksum), &Context::getBelChecksum, pass_through<uint32_t>,
                   conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelChecksum");
     fn_wrapper_3a_v<Context, decltype(&Context::bindBel), &Context::bindBel, conv_from_str<BelId>,
-                    conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindBel");
+                    addr_and_unwrap<CellInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindBel");
     fn_wrapper_1a_v<Context, decltype(&Context::unbindBel), &Context::unbindBel, conv_from_str<BelId>>::def_wrap(
             ctx_cls, "unbindBel");
-    fn_wrapper_1a<Context, decltype(&Context::getBoundBelCell), &Context::getBoundBelCell, conv_to_str<IdString>,
+    fn_wrapper_1a<Context, decltype(&Context::getBoundBelCell), &Context::getBoundBelCell, deref_and_wrap<CellInfo>,
                   conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell");
     fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell,
-                  conv_to_str<IdString>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
+                  deref_and_wrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
     fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels, wrap_context<BelRange>>::def_wrap(ctx_cls,
                                                                                                              "getBels");
 
@@ -88,15 +88,15 @@ void arch_wrap_python()
     fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>,
                   conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum");
     fn_wrapper_3a_v<Context, decltype(&Context::bindWire), &Context::bindWire, conv_from_str<WireId>,
-                    conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire");
+                    addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire");
     fn_wrapper_1a_v<Context, decltype(&Context::unbindWire), &Context::unbindWire, conv_from_str<WireId>>::def_wrap(
             ctx_cls, "unbindWire");
     fn_wrapper_1a<Context, decltype(&Context::checkWireAvail), &Context::checkWireAvail, pass_through<bool>,
                   conv_from_str<WireId>>::def_wrap(ctx_cls, "checkWireAvail");
-    fn_wrapper_1a<Context, decltype(&Context::getBoundWireNet), &Context::getBoundWireNet, conv_to_str<IdString>,
+    fn_wrapper_1a<Context, decltype(&Context::getBoundWireNet), &Context::getBoundWireNet, deref_and_wrap<NetInfo>,
                   conv_from_str<WireId>>::def_wrap(ctx_cls, "getBoundWireNet");
     fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet,
-                  conv_to_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet");
+                  deref_and_wrap<NetInfo>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet");
 
     fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires, wrap_context<WireRange>>::def_wrap(
             ctx_cls, "getWires");
@@ -106,15 +106,15 @@ void arch_wrap_python()
     fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>,
                   conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum");
     fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>,
-                    conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip");
+                    addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip");
     fn_wrapper_1a_v<Context, decltype(&Context::unbindPip), &Context::unbindPip, conv_from_str<PipId>>::def_wrap(
             ctx_cls, "unbindPip");
     fn_wrapper_1a<Context, decltype(&Context::checkPipAvail), &Context::checkPipAvail, pass_through<bool>,
                   conv_from_str<PipId>>::def_wrap(ctx_cls, "checkPipAvail");
-    fn_wrapper_1a<Context, decltype(&Context::getBoundPipNet), &Context::getBoundPipNet, conv_to_str<IdString>,
+    fn_wrapper_1a<Context, decltype(&Context::getBoundPipNet), &Context::getBoundPipNet, deref_and_wrap<NetInfo>,
                   conv_from_str<PipId>>::def_wrap(ctx_cls, "getBoundPipNet");
     fn_wrapper_1a<Context, decltype(&Context::getConflictingPipNet), &Context::getConflictingPipNet,
-                  conv_to_str<IdString>, conv_from_str<PipId>>::def_wrap(ctx_cls, "getConflictingPipNet");
+                  deref_and_wrap<NetInfo>, conv_from_str<PipId>>::def_wrap(ctx_cls, "getConflictingPipNet");
 
     fn_wrapper_1a<Context, decltype(&Context::getPipsDownhill), &Context::getPipsDownhill, wrap_context<PipRange>,
                   conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsDownhill");
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 543d7b35..979a274d 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -291,7 +291,7 @@ void write_asc(const Context *ctx, std::ostream &out)
     }

     // Set pips

     for (auto pip : ctx->getPips()) {

-        if (ctx->pip_to_net[pip.index] != IdString()) {

+        if (ctx->pip_to_net[pip.index] != nullptr) {

             const PipInfoPOD &pi = ci.pip_data[pip.index];

             const SwitchInfoPOD &swi = bi.switches[pi.switch_index];

             int sw_bel_idx = swi.bel;

@@ -310,7 +310,7 @@ void write_asc(const Context *ctx, std::ostream &out)
 

                 WireId permWire;

                 for (auto permPip : ctx->getPipsUphill(ctx->getPipSrcWire(pip))) {

-                    if (ctx->getBoundPipNet(permPip) != IdString()) {

+                    if (ctx->getBoundPipNet(permPip) != nullptr) {

                         permWire = ctx->getPipSrcWire(permPip);

                     }

                 }

@@ -384,7 +384,7 @@ void write_asc(const Context *ctx, std::ostream &out)
             for (int i = 0; i < 4; i++) {

                 WireId lut_wire = ctx->getBelPinWire(bel, PortPin(PIN_I0 + i));

                 for (auto pip : ctx->getPipsUphill(lut_wire)) {

-                    if (ctx->getBoundPipNet(pip) != IdString()) {

+                    if (ctx->getBoundPipNet(pip) != nullptr) {

                         std::string name = ci.wire_data[ctx->getPipSrcWire(pip).index].name.get();

                         switch (name.back()) {

                         case '0':

@@ -458,8 +458,8 @@ void write_asc(const Context *ctx, std::ostream &out)
             NPNR_ASSERT(iez != -1);

 

             bool input_en = false;

-            if ((ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_0).index] != IdString()) ||

-                (ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_1).index] != IdString())) {

+            if ((ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_0).index] != nullptr) ||

+                (ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_1).index] != nullptr)) {

                 input_en = true;

             }

 

@@ -618,7 +618,7 @@ void write_asc(const Context *ctx, std::ostream &out)
     }

     // Set config bits in unused IO and RAM

     for (auto bel : ctx->getBels()) {

-        if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_SB_IO) {

+        if (ctx->bel_to_cell[bel.index] == nullptr && ctx->getBelType(bel) == TYPE_SB_IO) {

             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];

             const BelInfoPOD &beli = ci.bel_data[bel.index];

             int x = beli.x, y = beli.y, z = beli.z;

@@ -633,7 +633,7 @@ void write_asc(const Context *ctx, std::ostream &out)
                 set_ie_bit_logical(ctx, ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), true);

                 set_ie_bit_logical(ctx, ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), false);

             }

-        } else if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_ICESTORM_RAM) {

+        } else if (ctx->bel_to_cell[bel.index] == nullptr && ctx->getBelType(bel) == TYPE_ICESTORM_RAM) {

             const BelInfoPOD &beli = ci.bel_data[bel.index];

             int x = beli.x, y = beli.y;

             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB];

@@ -751,9 +751,9 @@ void write_asc(const Context *ctx, std::ostream &out)
     // Write symbols

     // const bool write_symbols = 1;

     for (auto wire : ctx->getWires()) {

-        IdString net = ctx->getBoundWireNet(wire);

-        if (net != IdString())

-            out << ".sym " << wire.index << " " << net.str(ctx) << std::endl;

+        NetInfo *net = ctx->getBoundWireNet(wire);

+        if (net != nullptr)

+            out << ".sym " << wire.index << " " << net->name.str(ctx) << std::endl;

     }

 }

 

@@ -825,7 +825,7 @@ void read_config(Context *ctx, std::istream &in, chipconfig_t &config)
 

                 WireId wire;

                 wire.index = wireIndex;

-                ctx->bindWire(wire, netName, STRENGTH_WEAK);

+                ctx->bindWire(wire, ctx->nets.at(netName).get(), STRENGTH_WEAK);

             }

         } else if (line_nr >= 0 && strlen(buffer) > 0) {

             if (line_nr > int(config.at(tile_y).at(tile_x).size() - 1))

@@ -869,7 +869,7 @@ bool read_asc(Context *ctx, std::istream &in)
                 isUsed &= !(bool(cbit) ^ val);

             }

             if (isUsed) {

-                IdString net = ctx->wire_to_net[pi.dst];

+                NetInfo *net = ctx->wire_to_net[pi.dst];

                 WireId wire;

                 wire.index = pi.dst;

                 ctx->unbindWire(wire);

@@ -896,7 +896,7 @@ bool read_asc(Context *ctx, std::istream &in)
                     std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));

                     IdString name = created->name;

                     ctx->cells[name] = std::move(created);

-                    ctx->bindBel(bel, name, STRENGTH_WEAK);

+                    ctx->bindBel(bel, ctx->cells[name].get(), STRENGTH_WEAK);

                     // TODO: Add port mapping to nets and assign values of properties

                 }

             }

@@ -916,7 +916,7 @@ bool read_asc(Context *ctx, std::istream &in)
                     std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_IO"));

                     IdString name = created->name;

                     ctx->cells[name] = std::move(created);

-                    ctx->bindBel(bel, name, STRENGTH_WEAK);

+                    ctx->bindBel(bel, ctx->cells[name].get(), STRENGTH_WEAK);

                     // TODO: Add port mapping to nets and assign values of properties

                 }

             }

@@ -933,35 +933,35 @@ bool read_asc(Context *ctx, std::istream &in)
                                 std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));

                                 IdString name = created->name;

                                 ctx->cells[name] = std::move(created);

-                                ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

+                                ctx->bindBel(belpin.bel, ctx->cells[name].get(), STRENGTH_WEAK);

                                 // TODO: Add port mapping to nets

                             }

                             if (ctx->getBelType(belpin.bel) == TYPE_SB_IO) {

                                 std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_IO"));

                                 IdString name = created->name;

                                 ctx->cells[name] = std::move(created);

-                                ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

+                                ctx->bindBel(belpin.bel, ctx->cells[name].get(), STRENGTH_WEAK);

                                 // TODO: Add port mapping to nets

                             }

                             if (ctx->getBelType(belpin.bel) == TYPE_SB_GB) {

                                 std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_GB"));

                                 IdString name = created->name;

                                 ctx->cells[name] = std::move(created);

-                                ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

+                                ctx->bindBel(belpin.bel, ctx->cells[name].get(), STRENGTH_WEAK);

                                 // TODO: Add port mapping to nets

                             }

                             if (ctx->getBelType(belpin.bel) == TYPE_SB_WARMBOOT) {

                                 std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_WARMBOOT"));

                                 IdString name = created->name;

                                 ctx->cells[name] = std::move(created);

-                                ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

+                                ctx->bindBel(belpin.bel, ctx->cells[name].get(), STRENGTH_WEAK);

                                 // TODO: Add port mapping to nets

                             }

                             if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LFOSC) {

                                 std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC"));

                                 IdString name = created->name;

                                 ctx->cells[name] = std::move(created);

-                                ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

+                                ctx->bindBel(belpin.bel, ctx->cells[name].get(), STRENGTH_WEAK);

                                 // TODO: Add port mapping to nets

                             }

                         }

@@ -975,17 +975,17 @@ bool read_asc(Context *ctx, std::istream &in)
                     PortPin pin = ctx->portPinFromId(port.first);

                     WireId wire = ctx->getBelPinWire(cell.second->bel, pin);

                     if (wire != WireId()) {

-                        IdString name = ctx->getBoundWireNet(wire);

-                        if (name != IdString()) {

-                            port.second.net = ctx->nets[name].get();

+                        NetInfo *net = ctx->getBoundWireNet(wire);

+                        if (net != nullptr) {

+                            port.second.net = net;

                             PortRef ref;

                             ref.cell = cell.second.get();

                             ref.port = port.second.name;

 

                             if (port.second.type == PORT_OUT)

-                                ctx->nets[name]->driver = ref;

+                                net->driver = ref;

                             else

-                                ctx->nets[name]->users.push_back(ref);

+                                net->users.push_back(ref);

                         }

                     }

                 }