Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Merge pull request #79 from YosysHQ/ice40lvds | Clifford Wolf | 2018-09-25 | 8 | -13/+88 |
|\ | | | | | ice40: Adding LVDS input support | ||||
| * | ice40: LVDS input bitstream support | David Shah | 2018-09-24 | 1 | -4/+48 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | ice40: Tristate IO support fixes | David Shah | 2018-09-24 | 3 | -6/+10 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | ice40: Validity check for LVDS IO | David Shah | 2018-09-24 | 4 | -0/+29 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | ice40: Remove obsolete belType member | David Shah | 2018-09-24 | 3 | -3/+1 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | Merge pull request #76 from YosysHQ/plloutglobal_fix | Clifford Wolf | 2018-09-25 | 2 | -2/+38 |
|\ \ | | | | | | | Add needed PLLOUTGLOBAL ports and mapped it | ||||
| * | | Added required checks for PLL and fixed messages eol | Miodrag Milanovic | 2018-09-19 | 1 | -3/+31 |
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| * | | Add needed PLLOUTGLOBAL ports and mapped it properly | Miodrag Milanovic | 2018-09-12 | 2 | -0/+8 |
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* / | ice40: Fix carry packer bug | David Shah | 2018-09-25 | 1 | -2/+2 |
|/ | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Merge pull request #56 from YosysHQ/q3k/issue-55 | Serge Bazanski | 2018-08-19 | 2 | -12/+28 |
|\ | | | | | ice40: make PLL packing more robust | ||||
| * | ice40: make PLL packing more robust | Sergiusz Bazanski | 2018-08-19 | 2 | -12/+28 |
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* | | Add more missing iCE40 gfx (LP/HX is complete now) | Clifford Wolf | 2018-08-19 | 3 | -4/+47 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add iCE40 gfx for carry chain pips and LUT cascade pips | Clifford Wolf | 2018-08-19 | 1 | -5/+43 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Fix iCE40 pip gfx for pips on the top edge of a switchbox | Clifford Wolf | 2018-08-19 | 1 | -5/+5 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add iCE40 gfx for IO span-4 corners | Clifford Wolf | 2018-08-19 | 3 | -3/+36 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add iCE40 gfx for span-4 wires between IO tiles | Clifford Wolf | 2018-08-19 | 5 | -7/+126 |
|/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge pull request #47 from YosysHQ/settings_propagate | Clifford Wolf | 2018-08-18 | 4 | -16/+5 |
|\ | | | | | Use settings for placer1 and router1 | ||||
| * | Save settings and give nicer names to some | Miodrag Milanovic | 2018-08-10 | 2 | -3/+3 |
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| * | Use settings for placer1 and router1 | Miodrag Milanovic | 2018-08-09 | 2 | -13/+2 |
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* | | Add iCE40 gfx for wires connecting fabric tiles and IO tiles | Clifford Wolf | 2018-08-18 | 4 | -2/+261 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Improve iCE40 gfx for IO tiles and RAM tiles | Clifford Wolf | 2018-08-18 | 5 | -23/+243 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add ice40 wire attributes (grid position, segment list) | Clifford Wolf | 2018-08-18 | 3 | -18/+45 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Merge branch 'master' of github.com:YosysHQ/nextpnr into archattr | Clifford Wolf | 2018-08-18 | 1 | -4/+6 |
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| * | | do not break if there are no nets loaded from sym section | Miodrag Milanovic | 2018-08-18 | 1 | -4/+6 |
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* | | | Add Arch attrs API | Clifford Wolf | 2018-08-14 | 1 | -0/+18 |
|/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Merge remote-tracking branch 'origin/master' into placer_speedup | Eddie Hung | 2018-08-10 | 1 | -1/+11 |
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| * | Merge pull request #42 from YosysHQ/floorplan | David Shah | 2018-08-09 | 1 | -1/+11 |
| |\ | | | | | | | Add basic data structures for floorplanning | ||||
| | * | Add pip locations | Clifford Wolf | 2018-08-09 | 1 | -1/+11 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of ↵ | Eddie Hung | 2018-08-10 | 3 | -17/+18 |
| | | | | | | | | | | | | std::array | ||||
* | | | Make containers static | Eddie Hung | 2018-08-09 | 1 | -5/+7 |
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* | | ice40: Speedup Arch::predictDelay() with pass-by-ref | Eddie Hung | 2018-08-08 | 1 | -1/+1 |
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* | | Use settings for json and pcf | Miodrag Milanovic | 2018-08-08 | 4 | -8/+12 |
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* | Merge branch 'master' of github.com:YosysHQ/nextpnr into constids | Clifford Wolf | 2018-08-08 | 5 | -389/+270 |
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| * | Merge pull request #44 from YosysHQ/improve_timing_spec | David Shah | 2018-08-08 | 2 | -32/+89 |
| |\ | | | | | | | Speed up budget allocator using topographical ordering and update cell timing API | ||||
| | * | ice40: Add error for unknown cell type when getting timing info | David Shah | 2018-08-08 | 1 | -1/+3 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | Arch API: Removing Arch::isIOCell | David Shah | 2018-08-08 | 2 | -4/+0 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | ice40: Add timing arcs through global buffers | David Shah | 2018-08-08 | 1 | -0/+4 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | timing: Debugging implementation of new timing API | David Shah | 2018-08-08 | 1 | -1/+1 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | ice40: Timing arch fix | David Shah | 2018-08-08 | 1 | -3/+17 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | timing: Update to new use API (currently broken) | David Shah | 2018-08-08 | 1 | -2/+2 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | Arch API: New specification for timing port classes | David Shah | 2018-08-08 | 2 | -22/+52 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | clangformat | Eddie Hung | 2018-08-06 | 2 | -16/+20 |
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| | * | Merge branch 'master' into assign_budget_speedup | Eddie Hung | 2018-08-06 | 1 | -2/+17 |
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| | * | | Add new Arch::isIOCell() API function | Eddie Hung | 2018-08-06 | 2 | -0/+7 |
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| * | | | Moved option to common | Miodrag Milanovic | 2018-08-08 | 1 | -1/+0 |
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| * | | | clangformat | Miodrag Milanovic | 2018-08-08 | 1 | -4/+4 |
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| * | | | Merge remote-tracking branch 'origin/master' into common_main | Miodrag Milanovic | 2018-08-08 | 5 | -100/+114 |
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | # Conflicts: # ecp5/main.cc # ice40/main.cc | ||||
| * | | | Added project loader | Miodrag Milanovic | 2018-08-06 | 2 | -0/+72 |
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| * | | | Fix message for pcf loading | Miodrag Milanovic | 2018-08-05 | 1 | -1/+1 |
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| * | | | Added command parser and common implementation | Miodrag Milanovic | 2018-08-05 | 1 | -355/+111 |
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