aboutsummaryrefslogtreecommitdiffstats
path: root/fpga_interchange
Commit message (Collapse)AuthorAgeFilesLines
* netlist: Add PseudoCell APIgatecat2022-07-081-3/+3
| | | | | | | | | | | | | | | When implementing concepts such as partition pins or deliberately split nets, there's a need for something that looks like a cell (starts/ends routing with pins on nets, has timing data) but isn't mapped to a fixed bel in the architecture, but instead can have pin mappings defined at runtime. The PseudoCell allows this by providing an alternate, virtual-function based API for such cells. When a cell has `pseudo_cell` used, instead of calling functions such as getBelPinWire, getBelLocation or getCellDelay in the Arch API; such data is provided by the cell itself, fully flexible at runtime regardless of arch, via methods on the PseudoCell implementation.
* Added fallback to VCC as the preferred constant if the architecture does not ↵Maciej Kurc2022-05-123-6/+20
| | | | | | specify one. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added tying unused LUT pins to preferred constant instead of VccMaciej Kurc2022-05-111-2/+8
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Generalized representation of unused LUT pins connectionsMaciej Kurc2022-05-115-58/+160
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* interchange: Don't hold reference to visit in global routingKrzysztof Boronski2022-03-111-1/+1
| | | | Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
* clangformatgatecat2022-03-092-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: lut map cache: remove hardcoded valuesAlessandro Comodi2022-03-044-12/+21
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Switch to potentially-sparse net users arraygatecat2022-02-273-22/+14
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New member functions to replace design_utilsgatecat2022-02-183-5/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-162-6/+4
|
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-4/+6
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: fix uninitialized memory bug in cluster placementAlessandro Comodi2021-10-011-1/+1
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Fix compile warningsgatecat2021-09-282-6/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix small isses and code formattingMaciej Dudek2021-09-274-146/+148
| | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* Break up macro_cluster_placement into smaller functionsMaciej Dudek2021-09-241-20/+33
| | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* Fix AC-3 algorithmMaciej Dudek2021-09-231-9/+17
| | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* Improve macro cluster placementMaciej Dudek2021-09-231-235/+41
| | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* Change Cluster placement algorithmMaciej Dudek2021-09-233-123/+133
| | | | | | | Use physical placement from device DB It should reduce runtime Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* Adding MacroCell placementMaciej Dudek2021-09-233-17/+350
| | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* Adding support for MacroCellsMaciej Dudek2021-09-234-4/+382
|
* interchange: xdc: add more not_implemented commandsAlessandro Comodi2021-09-081-0/+2
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: xdc: add common not_implemented functionAlessandro Comodi2021-09-071-5/+18
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* clangformatgatecat2021-09-061-2/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: clusters: fix other cluster allowance checks in same siteAlessandro Comodi2021-08-311-7/+2
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: entirely disable cache when binding site routingAlessandro Comodi2021-08-311-6/+6
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: disallow placing cells on sites with clustersAlessandro Comodi2021-08-272-4/+22
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #780 from YosysHQ/gatecat/fix-io-invgatecat2021-07-261-13/+32
|\ | | | | interchange: Search backwards for IO macro placements, too
| * interchange: Search backwards for IO macro placements, toogatecat2021-07-261-13/+32
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | interchange: Don't attempt to import instances as modulesgatecat2021-07-261-5/+0
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Check IO validity after all are placedgatecat2021-07-231-6/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #757 from antmicro/lut-mapping-cachegatecat2021-07-228-74/+510
|\ | | | | interchange: Add caching of site LUT mapping solution
| * Added an option to disable the LUT mapping cacheMaciej Kurc2021-07-225-8/+16
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added more code comments, formatted the codeMaciej Kurc2021-07-226-123/+124
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added computing and reporting LUT mapping cache sizeMaciej Kurc2021-07-162-0/+37
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Fixed assertion typosMaciej Kurc2021-07-161-2/+2
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Migrated C arrays to std::array containers.Maciej Kurc2021-07-162-9/+31
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * LUT mapping ceche optimizations 2Maciej Kurc2021-07-163-93/+17
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * LUT mapping cache optimizations 1Maciej Kurc2021-07-162-32/+48
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Working site LUT mapping cacheMaciej Kurc2021-07-167-42/+470
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Add dummy function to parse creat_clock in XDC filesMaciej Dudek2021-07-211-0/+7
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | Merge pull request #767 from YosysHQ/gatecat/ic-pref-constgatecat2021-07-201-1/+10
|\ \ | | | | | | interchange: Fix preferred constant handling when canInvert
| * | interchange: Fix preferred constant handling when canInvertgatecat2021-07-201-1/+10
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | interchange: disallow pseudo-pip on same nets if tile has lutsAlessandro Comodi2021-07-151-8/+18
|/ / | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | [interchange] Update chipdb and python-fpga-interchange versionsMaciej Dudek2021-07-141-1/+1
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | interchange: xdc and place constr: address review commentsAlessandro Comodi2021-07-122-16/+13
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | interchange: xdc: add get_cells commandAlessandro Comodi2021-07-121-13/+70
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | interchange: add constraints constraints application routineAlessandro Comodi2021-07-123-0/+106
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | interchange: Skip IO ports in dedicated routing checkgatecat2021-07-121-0/+8
| | | | | | | | | | | | These have already been dealt with in arch_pack_io Signed-off-by: gatecat <gatecat@ds0.me>
* | interchange: Debug IO port validity check failuresgatecat2021-07-122-3/+5
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDSgatecat2021-07-121-3/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 17:18:33 +0000