diff options
| author | gatecat <gatecat@ds0.me> | 2022-02-18 10:52:37 +0000 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2022-02-18 11:13:18 +0000 |
| commit | 6a32aca4ac8705b637943c236cedd2f36422fb21 (patch) | |
| tree | 28483964fb3c92bc104ab6162d1c9196651ced26 /fpga_interchange | |
| parent | 61d1db16be2c68cf6ae8b4d2ff3266b5c7086ad2 (diff) | |
| download | nextpnr-6a32aca4ac8705b637943c236cedd2f36422fb21.tar.gz nextpnr-6a32aca4ac8705b637943c236cedd2f36422fb21.tar.bz2 nextpnr-6a32aca4ac8705b637943c236cedd2f36422fb21.zip | |
refactor: New member functions to replace design_utils
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/arch_pack_clusters.cc | 2 | ||||
| -rw-r--r-- | fpga_interchange/macros.cc | 6 | ||||
| -rw-r--r-- | fpga_interchange/site_router.cc | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/fpga_interchange/arch_pack_clusters.cc b/fpga_interchange/arch_pack_clusters.cc index b003812e..31e0522b 100644 --- a/fpga_interchange/arch_pack_clusters.cc +++ b/fpga_interchange/arch_pack_clusters.cc @@ -901,7 +901,7 @@ void Arch::prepare_cluster(const ClusterPOD *cluster, uint32_t index) // reachable due to the fixed dedicated interconnect. // E.g.: The CI input of carry chains in 7series corresponds to the CIN bel port, // which can only be connected to the COUT output of the tile below. - disconnect_port(ctx, ci, sink_port); + ci->disconnectPort(sink_port); } } diff --git a/fpga_interchange/macros.cc b/fpga_interchange/macros.cc index aa7d3184..8f7f8231 100644 --- a/fpga_interchange/macros.cc +++ b/fpga_interchange/macros.cc @@ -99,9 +99,9 @@ void Arch::expand_macros() // TODO: case of multiple top level ports on the same net? NPNR_ASSERT(net == nullptr); // Use the corresponding pre-expansion port net - net = get_net_or_empty(cell, IdString(net_port.port)); + net = cell->getPort(IdString(net_port.port)); // Disconnect the original port pre-expansion - disconnect_port(ctx, cell, IdString(net_port.port)); + cell->disconnectPort(IdString(net_port.port)); } // If not on a top level port, create a new net if (net == nullptr) @@ -115,7 +115,7 @@ void Arch::expand_macros() ctx->cells.at(derived_name(ctx, cell->name, IdString(net_port.instance))).get(); inst_cell->ports[port_name].name = port_name; inst_cell->ports[port_name].type = PortType(net_port.dir); - connect_port(ctx, net, inst_cell, port_name); + inst_cell->connectPort(port_name, net); } } diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc index 08e950e2..4e3d460a 100644 --- a/fpga_interchange/site_router.cc +++ b/fpga_interchange/site_router.cc @@ -953,7 +953,7 @@ static void apply_constant_routing(Context *ctx, const SiteArch &site_arch, NetI new_cell->belStrength = STRENGTH_PLACER; ctx->tileStatus.at(inverting_bel.tile).boundcells[inverting_bel.index] = new_cell; - connect_port(ctx, net_before_inverter, new_cell, id_I); + new_cell->connectPort(id_I, net_before_inverter); // The original BEL pin is now routed, but only through the inverter. // Because the cell/net model doesn't allow for multiple source pins |