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authorgatecat <gatecat@ds0.me>2021-07-26 15:36:20 +0100
committergatecat <gatecat@ds0.me>2021-07-26 15:36:20 +0100
commitc74f0d32395283c33f4d71dc1a6ca461eef616e1 (patch)
tree921689fd155237d7079c11d86deb29ef223004ee /fpga_interchange
parent6be26fbde75bf5828d47457df2af10747599711a (diff)
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interchange: Don't attempt to import instances as modules
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange')
-rw-r--r--fpga_interchange/fpga_interchange.cpp5
1 files changed, 0 insertions, 5 deletions
diff --git a/fpga_interchange/fpga_interchange.cpp b/fpga_interchange/fpga_interchange.cpp
index 1c6e6ce8..671b29f1 100644
--- a/fpga_interchange/fpga_interchange.cpp
+++ b/fpga_interchange/fpga_interchange.cpp
@@ -808,11 +808,6 @@ struct LogicalNetlistImpl
template <typename TFunc> void foreach_module(TFunc Func) const
{
- for (const auto &cell_inst : root.getInstList()) {
- ModuleReader module(this, cell_inst, /*is_top=*/false);
- Func(strings.at(cell_inst.getName()), module);
- }
-
auto top = root.getTopInst();
ModuleReader top_module(this, top, /*is_top=*/true);
Func(strings.at(top.getName()), top_module);