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path: root/fpga_interchange/arch.h
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* clangformatgatecat2021-04-121-3/+3
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-061-0/+3
* [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-061-5/+1
* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-061-0/+1
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-061-2/+14
* interchange: Fix illegal placementsgatecat2021-03-301-6/+5
* Implement debugging tools for site router.Keith Rothman2021-03-251-0/+2
* Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-251-1/+0
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-0/+13
* [FPGA interchange] Small fix to get_net_type.Keith Rothman2021-03-251-3/+8
* Merge pull request #644 from litghost/add_global_buffersgatecat2021-03-231-1/+13
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| * [FPGA interchange] Add support for global buffers from chipdb.Keith Rothman2021-03-231-1/+13
* | Merge pull request #643 from litghost/id_constantsgatecat2021-03-231-0/+2
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| * [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-231-0/+2
* | Initial version of inverter logic.Keith Rothman2021-03-231-0/+6
* | Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-231-0/+2
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* Initial lookahead for FPGA interchange.Keith Rothman2021-03-231-0/+8
* Merge pull request #637 from litghost/refine_site_routergatecat2021-03-221-0/+3
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| * Rework FPGA interchange site router.Keith Rothman2021-03-221-0/+3
* | Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-221-1/+1
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* Add pseudo pip data to chipdb (with schema bump).Keith Rothman2021-03-221-0/+14
* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-191-876/+160
* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-151-1/+1
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-7/+9
* Initial LUT rotation logic.Keith Rothman2021-02-261-1/+34
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-33/+21
* Working FF example now that constant merging is done.Keith Rothman2021-02-231-1/+3
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-5/+9
* Fix reference copy.Keith Rothman2021-02-231-6/+6
* Run "make clangformat".Keith Rothman2021-02-231-6/+8
* Initial working constant network support!Keith Rothman2021-02-231-4/+32
* Add initial constant network support to FPGA interchange arch.Keith Rothman2021-02-231-6/+46
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-1/+1
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-14/+4
* Fix sign mismatch.Keith Rothman2021-02-181-1/+1
* Add some utility methods for site instance access.Keith Rothman2021-02-181-5/+37
* Refactor "get only from iterator" to a utility.Keith Rothman2021-02-171-1/+5
* Continue fixes.Keith Rothman2021-02-171-10/+3
* Add initial site router.Keith Rothman2021-02-171-4/+58
* Working on standing up initial constraints system.Keith Rothman2021-02-171-14/+177
* Merge pull request #586 from litghost/add_cell_bel_mapping_onlygatecat2021-02-171-6/+105
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| * [FPGA Interchange] Add Cell -> BEL Pin maps.Keith Rothman2021-02-161-6/+105
* | Remove isValidBelForCellgatecat2021-02-161-11/+0
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* Add FPGA interchange frontend and backend.Keith Rothman2021-02-151-0/+10
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-151-0/+3
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| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+3
* | Add FPGA interchange XDC parser.Keith Rothman2021-02-121-1/+4
* | Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-2/+1
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* interchange: Base on ArchAPID. Shah2021-02-081-103/+134
* Add RelSlice::ssize and use it when comparing with signed ints.Keith Rothman2021-02-051-13/+14