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path: root/fpga_interchange/arch.h
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* api: add explain_invalid option to isBelLocationValidgatecat2022-12-071-1/+1
* refactor: ArcBounds -> BoundingBoxgatecat2022-12-071-2/+2
* api: Make NetInfo* of checkPipAvailForNet constgatecat2022-12-021-1/+1
* netlist: Add PseudoCell APIgatecat2022-07-081-3/+3
* clangformatgatecat2022-03-091-1/+1
* interchange: lut map cache: remove hardcoded valuesAlessandro Comodi2022-03-041-0/+5
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-1/+1
* Fix small isses and code formattingMaciej Dudek2021-09-271-4/+4
* Change Cluster placement algorithmMaciej Dudek2021-09-231-2/+0
* Adding MacroCell placementMaciej Dudek2021-09-231-1/+6
* Adding support for MacroCellsMaciej Dudek2021-09-231-0/+1
* interchange: clusters: fix other cluster allowance checks in same siteAlessandro Comodi2021-08-311-7/+2
* interchange: disallow placing cells on sites with clustersAlessandro Comodi2021-08-271-3/+20
* Merge pull request #757 from antmicro/lut-mapping-cachegatecat2021-07-221-0/+3
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| * Added an option to disable the LUT mapping cacheMaciej Kurc2021-07-221-1/+2
| * Working site LUT mapping cacheMaciej Kurc2021-07-161-0/+2
* | interchange: add constraints constraints application routineAlessandro Comodi2021-07-121-0/+3
* | interchange: reduce run-time to check dedicated interconnectAlessandro Comodi2021-07-081-1/+1
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* interchange: Allow pseudo pip wires to overlap with bound site wires on the s...gatecat2021-07-061-1/+2
* interchange: Improve search for PAD-attached belsgatecat2021-07-061-1/+2
* interchange: Track the macros that cells have been expanded fromgatecat2021-06-291-0/+1
* Fixing old emails and names in copyrightsgatecat2021-06-121-2/+2
* interchange: run clang formatterAlessandro Comodi2021-06-111-1/+1
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-111-14/+41
* Using hashlib in archesgatecat2021-06-021-11/+11
* interchange: Preliminary implementation of macro expansiongatecat2021-05-211-0/+2
* interchange: Adding a basic global buffer placergatecat2021-05-071-0/+2
* interchange: Initial global routing implementationgatecat2021-05-071-0/+6
* Add stub cluster API impl for remaining archesgatecat2021-05-061-0/+13
* interchange: Handle disconnected/missing cell pinsgatecat2021-04-191-0/+3
* clangformatgatecat2021-04-121-3/+3
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-061-0/+3
* [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-061-5/+1
* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-061-0/+1
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-061-2/+14
* interchange: Fix illegal placementsgatecat2021-03-301-6/+5
* Implement debugging tools for site router.Keith Rothman2021-03-251-0/+2
* Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-251-1/+0
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-0/+13
* [FPGA interchange] Small fix to get_net_type.Keith Rothman2021-03-251-3/+8
* Merge pull request #644 from litghost/add_global_buffersgatecat2021-03-231-1/+13
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| * [FPGA interchange] Add support for global buffers from chipdb.Keith Rothman2021-03-231-1/+13
* | Merge pull request #643 from litghost/id_constantsgatecat2021-03-231-0/+2
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| * [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-231-0/+2
* | Initial version of inverter logic.Keith Rothman2021-03-231-0/+6
* | Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-231-0/+2
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* Initial lookahead for FPGA interchange.Keith Rothman2021-03-231-0/+8
* Merge pull request #637 from litghost/refine_site_routergatecat2021-03-221-0/+3
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| * Rework FPGA interchange site router.Keith Rothman2021-03-221-0/+3
* | Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-221-1/+1
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