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authorKeith Rothman <537074+litghost@users.noreply.github.com>2021-03-19 18:26:00 -0700
committerKeith Rothman <537074+litghost@users.noreply.github.com>2021-03-22 09:54:49 -0700
commit32f2ec86c4b83d1e0f3c0982566ff4de30edebb3 (patch)
treef2d1a08d93cd9e9106b984cabfae23e768868b4b /fpga_interchange/arch.h
parent0f4014615cf9059332a75244a0ef5a9df4886ed0 (diff)
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Rework FPGA interchange site router.
The new site router should be robust to most situations, and isn't significantly slower with the use of caching. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'fpga_interchange/arch.h')
-rw-r--r--fpga_interchange/arch.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 6a3d7ad1..005bbb41 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -37,6 +37,7 @@
#include "chipdb.h"
#include "dedicated_interconnect.h"
#include "site_router.h"
+#include "site_routing_cache.h"
NEXTPNR_NAMESPACE_BEGIN
@@ -1037,6 +1038,8 @@ struct Arch : ArchAPI<ArchRanges>
std::regex verilog_hex_constant;
void read_lut_equation(DynamicBitarray<> *equation, const Property &equation_parameter) const;
bool route_vcc_to_unused_lut_pins();
+ mutable RouteNodeStorage node_storage;
+ mutable SiteRoutingCache site_routing_cache;
};
NEXTPNR_NAMESPACE_END