diff options
| author | gatecat <gatecat@ds0.me> | 2021-07-06 10:38:08 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-07-06 10:38:08 +0100 |
| commit | 31abefc8e49edce55fb42c99ac99b81e948d9004 (patch) | |
| tree | 11d7496a94275f54e98d566958890285e18a3104 /fpga_interchange/arch.h | |
| parent | 6fe071ad1d47c363f665995ae774edcd547e022d (diff) | |
| download | nextpnr-31abefc8e49edce55fb42c99ac99b81e948d9004.tar.gz nextpnr-31abefc8e49edce55fb42c99ac99b81e948d9004.tar.bz2 nextpnr-31abefc8e49edce55fb42c99ac99b81e948d9004.zip | |
interchange: Allow pseudo pip wires to overlap with bound site wires on the same net
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/arch.h')
| -rw-r--r-- | fpga_interchange/arch.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index b71b1d03..896a603a 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -576,7 +576,8 @@ struct Arch : ArchAPI<ArchRanges> const PipInfoPOD &pip_data = pip_info(chip_info, pip); for (int32_t wire_index : pip_data.pseudo_cell_wires) { wire.index = wire_index; - assign_net_to_wire(wire, net, "pseudo", /*require_empty=*/true); + if (getBoundWireNet(wire) != net) + assign_net_to_wire(wire, net, "pseudo", /*require_empty=*/true); } if (pip_data.pseudo_cell_wires.size() > 0) { |