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authorgatecat <gatecat@ds0.me>2021-12-19 16:41:34 +0000
committergatecat <gatecat@ds0.me>2021-12-19 17:15:15 +0000
commitddb084e9a8a0cba10536951236cde824526e8071 (patch)
treed03ba5688367cb476a06b19d04ca78d0352afce3 /fpga_interchange/arch.h
parent56d550733346000584b9490fac0953fe07124035 (diff)
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archapi: Use arbitrary rather than actual placement in predictDelay
This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/arch.h')
-rw-r--r--fpga_interchange/arch.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 482bf911..8bb2e2d1 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -700,7 +700,7 @@ struct Arch : ArchAPI<ArchRanges>
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const final;
- delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const final;
+ delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const final;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const final;
delay_t getDelayEpsilon() const final { return 20; }
delay_t getRipupDelayPenalty() const final { return 120; }