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* Merge pull request #653 from litghost/fix_site_pip_checkgatecat2021-03-301-7/+22
|\ | | | | [interchange] Fix site pip check for drivers.
| * [interchange] Fix site pip check for drivers.Keith Rothman2021-03-301-7/+22
|/ | | | | | Previous code allowed router to entire sites with no sinks. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #655 from YosysHQ/gatecat/alt-placer-fixgatecat2021-03-302-7/+8
|\ | | | | interchange: Fix illegal placements
| * interchange: Fix illegal placementsgatecat2021-03-302-7/+8
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix some IO FASM gengatecat2021-03-301-0/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix LIFCL-17 LRAM FASMgatecat2021-03-301-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix default IO configgatecat2021-03-291-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #651 from YosysHQ/gatecat/nexus-vccogatecat2021-03-291-3/+51
|\ | | | | nexus: Fix bank Vcco FASM
| * nexus: Fix bank Vcco FASMgatecat2021-03-291-3/+51
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | nexus: Default HF_OSC_EN to ENABLEDgatecat2021-03-291-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #645 from litghost/add_counter_and_ramgatecat2021-03-2923-337/+1221
|\ | | | | FPGA interchange: Add counter and ram tests
| * Update README with latest develpment progress.Keith Rothman2021-03-252-146/+39
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * interchange: Fix bug in site router where a bad solution isn't remove.Keith Rothman2021-03-251-3/+7
| | | | | | | | | | | | | | This resulted in valid site routing solutions being missed. Underlying bug was an off-by-one error when unwinding a failed solution. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Implement debugging tools for site router.Keith Rothman2021-03-257-23/+166
| | | | | | | | | | | | | | | | - Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire - Adds "explain_bel_status", which should be an exhaustive diagnostic of the status of a BEL placement. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add some FIXME's around VCC assumption in LUT logic.Keith Rothman2021-03-251-0/+17
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add targets to generate YAML outputs for DeviceResource files.Keith Rothman2021-03-251-0/+22
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-255-104/+174
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Fixup some of the re-mapping logic.Keith Rothman2021-03-252-27/+75
| | | | | | | | | | | | | | - Add IDEMPOTENT_CHECK define to perform some expected idempotent operations more than once to verify they work as expected. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-258-60/+460
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [FPGA interchange] Small fix to get_net_type.Keith Rothman2021-03-252-9/+14
| | | | | | | | | | | | | | If get_net_type was called before the driver was placed, it could return the wrong value. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Enable counter tests and add RAM tests.Keith Rothman2021-03-256-2/+284
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #649 from acomodi/add-archcheck-to-all-testsgatecat2021-03-263-9/+41
|\ \ | | | | | | interchange: add archcheck tests to all-device-test target
| * | gh-actions: better yosys caching based on versionAlessandro Comodi2021-03-262-6/+35
| | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * | interchange: add archcheck tests to all-device-test targetAlessandro Comodi2021-03-262-3/+6
|/ / | | | | | | | | | | | | This increases parallelism and should make the FPGA interchange CI faster Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #650 from YosysHQ/gatecat/nexus-17k-fixesgatecat2021-03-261-1/+4
|\ \ | |/ |/| nexus: Fix FASM gen for LIFCL-17
| * nexus: Fix FASM gen for LIFCL-17gatecat2021-03-261-1/+4
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #648 from YosysHQ/gatecat/nexus-get_pinsgatecat2021-03-251-7/+56
|\ | | | | nexus: Add support for get_pins PDC command
| * nexus: Add support for get_pins PDC commandgatecat2021-03-251-7/+56
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #628 from acomodi/add-interchange-devicesgatecat2021-03-2522-168/+450
|\ | | | | fpga_interchange: add more devices
| * gh-actions: use ccache and build tools before running testsAlessandro Comodi2021-03-252-40/+105
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * gh-actions: interchange: multiple jobs, one for each deviceAlessandro Comodi2021-03-244-8/+17
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: examples: remove unused makefilesAlessandro Comodi2021-03-242-99/+0
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: devices: bel_bucket_seeds -> device_configAlessandro Comodi2021-03-233-3/+3
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: added boards and group testing across multiple boardsAlessandro Comodi2021-03-2310-45/+155
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * gh-actions: remove multi-process arch generationAlessandro Comodi2021-03-231-1/+1
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * fpga_interchange: add test data for new architecturesAlessandro Comodi2021-03-233-0/+108
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * fpga_interchange: use higher java heap spaceAlessandro Comodi2021-03-233-3/+4
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * fpga_interchange: add more devicesAlessandro Comodi2021-03-238-3/+91
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #644 from litghost/add_global_buffersgatecat2021-03-235-11/+30
|\ | | | | [FPGA interchange] Add support for global buffers from chipdb.
| * [FPGA interchange] Add support for global buffers from chipdb.Keith Rothman2021-03-235-11/+30
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #643 from litghost/id_constantsgatecat2021-03-232-4/+27
|\ \ | | | | | | [FPGA interchange] Convert some string constants to IdString.
| * | [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-232-4/+27
| | | | | | | | | | | | | | | | | | Also add some optional diagnostic prints for cell -> BEL pin mapping. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Merge pull request #640 from litghost/inversion_logicgatecat2021-03-237-8/+131
|\ \ \ | | |/ | |/| Initial inverter logic for FPGA interchange
| * | Initial version of inverter logic.Keith Rothman2021-03-237-8/+131
| | | | | | | | | | | | | | | | | | | | | For now just implements some inspection capabilities, and the site router (for now) avoids inverted paths. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Merge pull request #639 from litghost/parameter_iterationgatecat2021-03-238-44/+446
|\| | | |/ |/| Update parameter processing based on new DeviceResources metadata
| * Update FPGA interchange chipdb to v4 with inverter data.Keith Rothman2021-03-231-1/+22
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-237-43/+415
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Update latest version of FPGA interchange schema.Keith Rothman2021-03-231-1/+10
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #642 from YosysHQ/gatecat/missing-cell-pingatecat2021-03-231-0/+3
|\ \ | |/ |/| interchange: Add nice error for missing cell pins
| * interchange: Add nice error for missing cell pinsgatecat2021-03-231-0/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-09 10:04:05 +0000