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| author | gatecat <gatecat@ds0.me> | 2021-03-23 16:34:10 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-23 16:34:10 +0000 |
| commit | b7bf2c706fcb24242b93b1993c8073d82d4028bb (patch) | |
| tree | c21a1e86a3ab3dcfb8c10f50912eb9a3c522ea7b | |
| parent | 4d8dcab1d3fba1799de7eb51be2dd7bd5dd2e53f (diff) | |
| parent | 79400756f5d9d9c751aea93d1071d95073751075 (diff) | |
| download | nextpnr-b7bf2c706fcb24242b93b1993c8073d82d4028bb.tar.gz nextpnr-b7bf2c706fcb24242b93b1993c8073d82d4028bb.tar.bz2 nextpnr-b7bf2c706fcb24242b93b1993c8073d82d4028bb.zip | |
Merge pull request #642 from YosysHQ/gatecat/missing-cell-pin
interchange: Add nice error for missing cell pins
| -rw-r--r-- | fpga_interchange/site_router.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc index c470f3f6..3252cac1 100644 --- a/fpga_interchange/site_router.cc +++ b/fpga_interchange/site_router.cc @@ -58,6 +58,9 @@ bool check_initial_wires(const Context *ctx, SiteInformation *site_info) for (CellInfo *cell : site_info->cells_in_site) { BelId bel = cell->bel; for (const auto &pin_pair : cell->cell_bel_pins) { + if (!cell->ports.count(pin_pair.first)) + log_error("Cell %s:%s is missing expected port %s\n", ctx->nameOf(cell), cell->type.c_str(ctx), + pin_pair.first.c_str(ctx)); const PortInfo &port = cell->ports.at(pin_pair.first); NPNR_ASSERT(port.net != nullptr); |